Home
  • 产品
  • 解决方案
  • 支持与培训
  • 公司
  • ZH CN
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • Japan - 日本語
    • Korea - 한국어
    • Taiwan - 繁體中文

尖端设计工具

  • 数字设计与签核
  • 定制 IC/模拟/ RF 设计
  • 系统设计与验证
  • IP
  • IC 封装设计与分析

创新系统设计

  • Multiphysics System Analysis
  • 嵌入式原型验证
  • PCB 设计与分析
  • Computational Fluid Dynamics

万物智能

  • AI / 机器学习
  • AI IP 产品

CADENCE云服务

VIEW ALL PRODUCTS

数字设计与签核

Cadence® 数字与签核解决方案, 提供快速的设计收敛和更出色的可预测性,助您实现功耗、性能和面积(PPA)目标。

PRODUCT CATEGORIES

  • 逻辑等效性检查
  • SoC Implementation and Floorplanning
  • 形式验证与功能 ECO
  • 低功耗验证
  • RTL 综合
  • 功耗分析
  • Constraints and CDC Signoff
  • 硅签核
  • 库表征
  • 可测性设计

FEATURED PRODUCTS

  • Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows
  • Voltus IC Power Integrity Solution

定制 IC/模拟/ RF 设计

Cadence® 定制、模拟和射频设计解决方案可以实现模块级和混合信号仿真、布线和特征参数提取等诸多日常任务的自动化,助您节省大量时间。

PRODUCT CATEGORIES

  • 电路设计
  • 电路仿真
  • 版图设计
  • 版图验证
  • 特征库提取
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-Fi Custom Power Integrity Solution
  • RESOURCES
  • Flows

Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • 调试纠错分析
  • Virtual Prototyping
  • Emulation and Prototyping
  • 形式化验证与静态验证
  • 验证规划与管理
  • 仿真
  • 软件驱动验证
  • 验证IP(VIP)
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • Denali Memory Interface and Storage IP
  • 112G/56G SerDes
  • PCIe and CXL
  • Tensilica Processor IP
  • Chiplet and D2D
  • Interface IP

RESOURCES

  • Discover PCIe

IC 封装设计与分析

提升先进封装、系统规划和多织构互操作性的效率和准确性,Cadence 封装实现工具可实现自动化和精准度。

PRODUCT CATEGORIES

  • IC 封装设计
  • IC封装设计流程
  • SI/PI 分析
  • SI/PI 分析点工具
  • 跨平台协同设计与分析

Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • 电磁求解器
  • 射频/微波设计
  • Signal and Power Integrity
  • 热求解器

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Solver Cloud
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Fidelity CFD
  • Sigrity Advanced SI
  • Celsius Advanced PTI
  • RESOURCES
  • System Analysis Center
  • System Analysis Resources Hub
  • AWR Free Trial

嵌入式原型验证

PCB 设计与分析

Cadence® PCB 设计解决方案更好地结合了组件设计和约束驱动流程的系统级仿真,实现更短、更加可预测的设计周期。

PRODUCT CATEGORIES

  • 原理图设计
  • PCB Layout
  • 库与设计数据管理
  • 模拟/混合信号仿真
  • SI/PI Analysis
  • SI/PI 分析点工具
  • 射频/微波设计
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • RESOURCES
  • What's New in Allegro
  • Advanced PCB Design & Analysis Blog
  • Flows

Computational Fluid Dynamics

AI / 机器学习

AI IP 产品

产业方案

  • 5G系统与子系统
  • 航天与国防
  • 汽车电子解决方案
  • Hyperscale Computing

技术方案

  • 3D-IC设计
  • 数字先进节点
  • AI / 机器学习
  • Arm-Based解决方案
  • Cloud 解决方案
  • Computational Fluid Dynamics
  • Functional Safety
  • 低功耗设计
  • 混合信号设计
  • 光电设计
  • 射频/微波
See how our customers create innovative products with Cadence

技术支持

  • 技术支持流程
  • 线上技术支持
  • 软件下载
  • 计算平台支持
  • 售后支持联络
  • 技术论坛

培训

  • 定制IC/模拟/设计
  • 设计语言及方法学
  • 数字设计与签核
  • IC封装
  • PCB设计
  • 系统设计与验证
  • Tensilica处理器IP
Stay up to date with the latest software 24/7 - Cadence Online Support Visit Now

公司介绍

  • 关于我们
  • 成功合作
  • 投资者关系
  • 管理团队
  • Computational Software
  • Alliances
  • 公司社会责任
  • Cadence大学计划

媒体中心

  • 会议活动
  • 新闻中心
  • 博客

企业文化与职业

  • Cadence文化与多样性
  • 招贤纳士
Learn how Intelligent System Design™ powers future technologies Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
ZH - China
  • US - English
  • Japan - 日本語
  • Korea - 한국어
  • Taiwan - 繁體中文
  • 产品
    • 尖端设计工具
      • 数字设计与签核
        • PRODUCT CATEGORIES
          • 逻辑等效性检查
          • SoC Implementation and Floorplanning
          • 形式验证与功能 ECO
          • 低功耗验证
          • RTL 综合
          • 功耗分析
          • Constraints and CDC Signoff
          • 硅签核
          • 库表征
          • 可测性设计
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 定制 IC/模拟/ RF 设计
        • PRODUCT CATEGORIES
          • 电路设计
          • 电路仿真
          • 版图设计
          • 版图验证
          • 特征库提取
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • 调试纠错分析
          • Virtual Prototyping
          • Emulation and Prototyping
          • 形式化验证与静态验证
          • 验证规划与管理
          • 仿真
          • 软件驱动验证
          • 验证IP(VIP)
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC 封装设计与分析
        • PRODUCT CATEGORIES
          • IC 封装设计
          • IC封装设计流程
          • SI/PI 分析
          • SI/PI 分析点工具
          • 跨平台协同设计与分析
    • 创新系统设计
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • 电磁求解器
          • 射频/微波设计
          • Signal and Power Integrity
          • 热求解器
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式原型验证
      • PCB 设计与分析
        • PRODUCT CATEGORIES
          • 原理图设计
          • PCB Layout
          • 库与设计数据管理
          • 模拟/混合信号仿真
          • SI/PI Analysis
          • SI/PI 分析点工具
          • 射频/微波设计
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Blog
          • Flows
      • Computational Fluid Dynamics
    • 万物智能
      • AI / 机器学习
      • AI IP 产品
    • CADENCE云服务
    • VIEW ALL PRODUCTS
  • 解决方案
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • Hyperscale Computing
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • AI / 机器学习
        • Arm-Based解决方案
        • Cloud 解决方案
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
  • 支持与培训
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
        • Tensilica处理器IP
  • 公司
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士

  • Home
  •   :  
  • 关于我们
  •   :  
  • Newsroom
  •   :  
  • News Releases
  •   :  
  • 10 Mar 2015

Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time

SAN JOSE, Calif., 09 Mar 2015

  • Provides typical 10 to 20 percent production-proven advantage in power, performance and area
  • First massively parallel implementation solution in the industry, enabling unprecedented speed and capacity
  • Supports advanced 16/14/10nm FinFET and established process nodes
  • Next-generation platform eases usability and boosts engineering productivity
Cadence Design Systems, Inc. (NASDAQ: CDNS) today unveiled Cadence® Innovus™ Implementation System, its next-generation physical implementation solution that enables system-on-chip (SoC) developers to deliver designs with best-in-class power, performance and area (PPA) while accelerating time to market. Driven by a massively parallel architecture with breakthrough optimization technologies, the Innovus Implementation System provides typically 10 to 20 percent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.

For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.

The Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realize maximum power/area savings while optimizing for a set target frequency. The key Innovus capabilities to achieve this include:
  • New GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/color-aware, enabling optimal pipeline placement, wirelength, utilization and PPA, and providing the best starting point for optimization
  • Advanced timing- and power-driven optimization that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance
  • Unique concurrent clock and datapath optimization that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power
  • Next-generation slack-driven routing with track-aware timing optimization that tackles signal integrity early on and improves post-route correlation
  • Full-flow multi-objective technology enables concurrent electrical and physical optimization to avoid local optima, resulting in the most globally optimal PPA
The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the industry's first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

In addition to providing best-in-class PPA and optimized turnaround time, the Innovus Implementation System offers a common user interface (UI) across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus™ Timing Signoff solution and Quantus™ QRC Extraction solution. Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customizable flow. Customers can also benefit from robust visualization and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.

"At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets," said Noel Hurley, general manager, CPU group, ARM. "We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target. Based on our results, we are confident that the new physical implementation solution can help our mutual customers deliver complex, advanced-node SoCs on time."

"Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimized area to deliver designs to the market before the competition can," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial turnaround time reduction versus competing solutions."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Innovus, Quantus and Tempus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other trademarks are the property of their respective owners.

Media Contacts

For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

A Great Place to Do Great Work!

Eighth year on the FORTUNE 100 list

Our Culture Join The Team

关注Cadence官方微信

We Chat QR Code
  • 产品
  • 定制 IC /模拟/ RF 设计
  • 数字设计与Signoff
  • IC 封装设计与分析
  • IP
  • PCB 设计与分析
  • 系统分析
  • 系统设计与验证
  • 所有产品
  • 公司
  • 关于我们
  • 管理团队
  • 投资者关系
  • 产业联盟
  • 就业机会
  • Cadence 学术网
  • Supplier
  • 媒体中心
  • Events
  • 新闻中心
  • Cadence 设计
  • 博客
  • 论坛
  • 联系我们
  • 普通咨询
  • 客户支持
  • 媒体中心
  • 全球办公室查找

关注Cadence官方微信

We Chat QR Code

关注Cadence官方微信

We Chat QR Code

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2022 Cadence Design Systems, Inc. All Rights Reserved.

沪ICP备18027754号 Terms of Use Privacy US Trademarks