Press Releases

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Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications Cadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s... Released Date: 02 Dec 2019
Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation National Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele... Released Date: 02 Dec 2019
Cadence全新面向芯片间互联UltraLink D2D PHY IP助力实现高性能和经济有效封装应用硅验证、高带宽、低延时助力Cadence将高性能计算IP产品组合扩展至AI/ML、5G、云计算和网络应用 … 已通过硅验证并已开始与客户洽谈相关合作支持基于有机基板的多芯片模块SoC 40Gbps线速度可实现高达1Tbps / mm的单向带宽无需前向纠错（FEC）即可实现低于10-15误码率（BER … 楷登电子（美国Cadence公司，Nasdaq … Released Date: 29 Nov 2019
Cadence’s John Wall to Present at Nasdaq 41st Investor Conference in London Mr. Wall will participate in a fireside chat in addition to hosting individual meetings with investors at the Nasdaq 41st Investor Conference on December 3, 2019 at The May Fair Hotel, London. Released Date: 18 Nov 2019
Cadence发布Tempus电源完整性签核方案 ——面向时序感知电压降分析 … 业界首款将STA与电源分析相结合的集成式电源完整性解决方案，可在7nm及更先进节点下实现更可靠、更全面的签核在不影响高阶节点低压设计签核质量的前提下，降低IR压降设计余量以优化功耗和面积利用专有无激励算法捕捉最坏情况下的功耗翻转情况，在不增加运行时间的前提下提高IR压降分析的可靠性帮助用户在流片前识别并自动修复 … Released Date: 15 Nov 2019
New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging Cadence announced the UltraLink D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments. Released Date: 13 Nov 2019
Cadence荣获4项2019年TSMC合作伙伴大奖 Cadence因与TSMC合作开发N6设计基础架构，SoIC设计解决方案，云服务解决方案和DSP IP获多项殊荣 … 楷登电子（美国Cadence公司，NASDAQ：CDNS）今日宣布，在TSMC 2019年开放创新平台®（OIP）生态系统论坛上荣获4项合作伙伴大奖 … Cadence在多个开发项目中的贡献而获奖，包括 … 基于云平台的TSMC OIP虚拟设计环境（VDE... Released Date: 31 Oct 2019
Cadence Presented with Four 2019 TSMC Partner of the Year Awards Cadence today announced that it has been presented with four TSMC Partner of the Year awards at the TSMC 2019 Open Innovation Platform® (OIP) Ecosystem Forum. Released Date: 30 Oct 2019
Cadence’s Nimish Modi to Present at 6th Annual Bernstein Technology Innovation Summit in New York, NY Mr. Modi will participate in a fireside chat in addition to hosting individual meetings with investors at the 6th Annual Bernstein Technology Innovation Summit on November 6, 2019 at the Westin NY Times Sq... Released Date: 25 Oct 2019
Cadence发布业界首款面向高性能计算的NVMe 1.4验证IP Cadence VIP支持 TripleCheck，可大幅缩短产品上市时间并支持下一代NVMe标准 … 楷登电子（美国Cadence公司，NASDAQ：CDNS）今日推出业内首款支持NVM Express 1.4（NVMe）协议的验证IP（VIP）产品 … 面向NVMe 1.4协议的Cadence® VIP可以助力设计师迅速、全面且更加省力地验证存储、数据中心和高性能 …... Released Date: 23 Oct 2019

Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications

Cadence Design Systems, Inc. and National Instruments Corporation announced that they have entered into a definitive agreement pursuant to which Cadence expects to acquire AWR Corporation, a wholly owned s...

Released Date: 02 Dec 2019

Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation

National Instruments Corporation and Cadence Design Systems, Inc. announced a system innovation strategic alliance to create an integrated design to test flow, leveraging reusable data and test IP from ele...

Released Date: 02 Dec 2019

Cadence全新面向芯片间互联UltraLink D2D PHY IP助力实现高性能和经济有效封装应用

硅验证、高带宽、低延时助力Cadence将高性能计算IP产品组合扩展至AI/ML、5G、云计算和网络应用 … 已通过硅验证并已开始与客户洽谈相关合作支持基于有机基板的多芯片模块SoC 40Gbps线速度可实现高达1Tbps / mm的单向带宽无需前向纠错（FEC）即可实现低于10-15误码率（BER … 楷登电子（美国Cadence公司，Nasdaq …

Released Date: 29 Nov 2019

Cadence’s John Wall to Present at Nasdaq 41st Investor Conference in London

Mr. Wall will participate in a fireside chat in addition to hosting individual meetings with investors at the Nasdaq 41st Investor Conference on December 3, 2019 at The May Fair Hotel, London.

Released Date: 18 Nov 2019

Cadence发布Tempus电源完整性签核方案

——面向时序感知电压降分析 … 业界首款将STA与电源分析相结合的集成式电源完整性解决方案，可在7nm及更先进节点下实现更可靠、更全面的签核在不影响高阶节点低压设计签核质量的前提下，降低IR压降设计余量以优化功耗和面积利用专有无激励算法捕捉最坏情况下的功耗翻转情况，在不增加运行时间的前提下提高IR压降分析的可靠性帮助用户在流片前识别并自动修复 …

Released Date: 15 Nov 2019

New Cadence UltraLink D2D PHY IP for Die-to-Die Connectivity Enables High-Performance Applications with Cost-Effective Packaging

Cadence announced the UltraLink D2D PHY IP, a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.

Released Date: 13 Nov 2019

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