AU2 : Automotive – The Changing Landscape

Simon Chang, Cadence

AU3 : Implementing ADAS and Infotainment SOC in advanced process nodes

Thomas Wong, Cadence

CUS1 : Analog/Mixed-Signal Technology Overview

Zhong Fan, Cadence

CUS2 : Meeting Quality and Reliability Requirements for Advanced-Node and Mission-Critical Applications

Rui Pan, Cadence

CUS3 : Analog Mixed-Signal UVM-Based Verification in Automotive Chip

Steven Xu, Analog Device

CUS4 : AMS Verification Method for NXP i.MX RT Product

Angela Liang, NXP Semiconductor
Sheng Bin, NXP Semiconductor
Xu Yang, NXP Semiconductor
Xu Jiagang, NXP Semiconductor
Li Mingxuan, NXP Semiconductor

CUS5 : Automatic Simulation Method for Functional Equivalence Check

Lu Liao, YMTC
候春源, YMTC
李跃平, YMTC
王美, YMTC

CUS6 : UMC 28HPC+ Analog/Mixed-Signal Reference Flow—Cadence Schematic to GDS

Kevin Tsai, Cadence

CUS7 : Introducing the Virtuoso RF Solution for RF System Design

Huanyan Liu, Cadence

CUS8 : Using Virtuoso ADE Verifier in Project Management and Project Regression

Bob Lv, Cadence

CUS9 : Fastest Design Closure with Accurate Parasitic Extraction

Hitendra Divecha, Cadence

DF2 : Tempus Hierarchical Techniques and Cloud Computing for STA Signoff and ECO

Marc Swinnen, Cadence

DF3 : Timing and Power Convergence on Mega Chip Using TSO

Wei Liu, Avera Semiconductor
Wenxing Jia, Avera Semiconductor
Hongwei Dai, Avera Semiconductor
Tim Helvey, Avera Semiconductor
Yang Yang, Avera Semiconductor

DF4 : A True Signoff Solution for Concurrent IR Drop and Timing in Voltus + Tempus

Jerry Zhao, Cadence

DF5 : 设计中电压降分析与优化

Qing Wang, Verisilicon
黄秋华, Verisilicon
金冬明, Verisilicon

DF6 : Robust Power Distribution Design with Cadence® Voltus™ PSI Analysis

Hongwei Dai, Avera Semiconductor
任玉超, Avera Semiconductor
Cindy Zhang, Avera Semiconductor
孟雪, Avera Semiconductor
Wei Liu, Avera Semiconductor

DF7 : InDesign Voltage-Drop Aware Optimization for Accelerating the Design Convergence

Chuck Chu, NVIDIA
Asia Li, NVIDIA
JOHNSON SHI, NVIDIA

DF8 : Electromigration Analysis of FinFET Self-Heating

Xiaojun Zhang, Cambricon
季昊, Cambricon

DI3 : A Comprehensive Power Optimization Practice on 14nm Mega Chips by Using Innovus Power Recovery and CCopt Engine

Wenxing Jia, Avera Semiconductor
Wei Liu, Avera Semiconductor
Cindy Zhang, Avera Semiconductor
Yang Yang, Avera Semiconductor
Hongwei Dai, Avera Semiconductor

DI4 : Interposer Design with Innovus Implementation System

Leqi Li, ZTE/SANECHIPS
任晓黎, ZTE/SANECHIPS
谢业磊, ZTE/SANECHIPS
庞健, ZTE/SANECHIPS
孙拓北, ZTE/SANECHIPS

DI5 : Low Power Clock Tree Buffer and Inverter Reduction in Innovus Implementation System

Glen Ge, NXP Semiconductor
付娟, NXP Semiconductor
王沛东, NXP Semiconductor
厉媛玥, NXP Semiconductor
王亚丽, NXP Semiconductor
赵文静, NXP Semiconductor

DI6 : 基于Innovus提升芯片性能的物理实现方法

Shaoxian Bian, 天津飞腾信息技术有限公司
栾晓琨, 天津飞腾信息技术有限公司
蒋剑锋, 天津飞腾信息技术有限公司
蔡准, Cadence
David He, 天津飞腾信息技术有限公司
翟飞雪, 天津飞腾信息技术有限公司

DI7 : Feedthrough of Very Large Scale Integrated Circuit Based on Innovus Implementation System

Yuebin Xu, ZTE/SANECHIPS

DI8 : 基于Innovus平台的云端训练AI芯片设计

Wade Lu, Enflame

DI9 : AI in P&R, Mixplacer Introduction

Necle Zhao, Broadcom

SP1 : True 3D Analysis of Large Geometries with Clarity 3D Solver

Jian Liu, Cadence

SP2 : Allegro Pulse and What’s New in Allegro 17.4 Release

Julian Sun, Cadence

SP3 : 2.5D Package Interposer Automatic Design Based on Allegro Package Designer

Cheng Zhang, GLOBALFOUNDRIES
Tan Lingyan, GLOBALFOUNDRIES
Zeng Lingyue, GLOBALFOUNDRIES

SP4 : Overcoming SI/PI Simulation Challenges of LP4/LP4X Interfaces on Mobile Applications

Nikki Xie, UniSOC

SP5 : 面对高速高密需求的软硬结合板的设计与仿真

Bruce Wu, EDADOC
肖勇超, EDADOC
黄刚, EDADOC
王辉东, EDADOC
Yali Cui, EDADOC

SP6 : PI Simulation Efficiency Improvement Case

Xiaoli Zhang, Ericsson
Guohua Wang, Ericsson

SP7 : SerDes Simulation Using IBIS AMI Model

Gary Wu, Teradyne

SP8 : 高速并行信号过孔间的串扰研究

Vector Cheng, NXP Semiconductor
朱凯, NXP Semiconductor
江勇, NXP Semiconductor
李文辉, NXP Semiconductor

SP9 : Automatic Extraction, Verification, and Optimization of 2D and 2.5D Packages

TianHong Lan, averasemi
Erik Breiland, averasemi
Eric Tremble, averasemi

SV1 : Optimizing Verification Throughput for Advanced Designs in a Connected World

Michael Young, Cadence

SV2 : Enhance LPDDR5 DRAM Controller Verification with Cadence LPDDR VIP

Mengru Si, MediaTek

SV3 : 基于硬件加速器的高性能芯片仿真与验证

Lei Wang, IMECAS
王晨光, IMECAS
吴斌, IMECAS

SV4 : Formal Practice in CPU Core Verification Using JasperGold Formal Verification Platform

Lei Wang, IMECAS
王晨光, IMECAS
吴斌, IMECAS

SV5 : Palladium PCIe Environment

Wei Li, Bitmain

SV6 : FSM Deadlock Hunt Case Study with JasperGold Superlint App

Jun Shen, GLOBALFOUNDRIES
徐茜, GLOBALFOUNDRIES
朱文, GLOBALFOUNDRIES
胡倩, GLOBALFOUNDRIES
刘军, GLOBALFOUNDRIES
陈言言, GLOBALFOUNDRIES
方海霞, GLOBALFOUNDRIES
江国范, GLOBALFOUNDRIES

SV7 : 浅谈Emulator在多媒体芯片开发中的应用

Jiguo Zeng, Goke

SV8 : Simplify PCIe RP Enumeration Verification Using VIP

Fangheng Yu, Avera Semiconductor
刘思颖, Avera Semiconductor
曹飞, Avera Semiconductor

SV9 : Real Number Modeling in Flash Memory Fullchip Validation

Lin Zhou, YMTC

TA3 : Low Latency Audio Streaming and Multi Connection Solution

谷石林, 欧思数码 Optek

TA4 : Tensilica HiFi DSP for TWS Solutions

Jeffrey Xu, Cadence

TIP2 : 整合AI产业链，促进算法高效落地

刘若水, 极视角 Extreme Vision

TIP3 : 智能感知与边缘计算

白震东, 臻识科技 Vision-Zenith

TIP4 : Deep Learning Optimization for Edge AI Device

Samuel Liu, Skymizer

TIP5 : 语音交互引领下的新计算平台

李智勇, 声智科技 SoundAI

TIP6 : XANC-芯云融合的新一代主动降噪技术

虞安波, 会听声学 HTAcoustics

TIP7 : 智能音箱的音频信号后处理及系统优化

李文烨, 索那声美 SONA Acoustic

TIP8 : 基于深度学习的新一代信号处理技术及其应用

时晓宽, 大象声科 Elevoc