If you have trouble reading this message, please click here.
Issue 1

Welcome to Issue 1 of the Cadence NewsLink
We hope you find this digest of news and other recently published information to be a useful resource and convenient way to keep up with what's new at Cadence.

Functional Verification

Verification IP (VIP)
Expanded Verification IP Portfolio - Product Info
OVM Compliant, Multi-Language Verification IP - Product Info
MIPI Verification IP Available Now - Product Info
VIP Following OVM Frees Users to Choose SystemVerilog and e - Blog
Metric Driven Verification, Methodology and Management
VMM Users — Welcome to the OVM! - Blog
Learn About MDV With Hands On Workshops - Blog
Maximize your Verification Throughput with Incisive Enterprise Manager - Product Info
'Team Specman' Blog exclusively for e and Specman - Blog
Michael Stellfox on Verification Methodology of all types - Blog
Adam Sherer on OVM - Blog
  Resources:  Product Info  |  Community  |  Events & Webinars

Visit us at DVCon 2009
February 24 - 26 — DoubleTree Hotel
San Jose, CA, Booth #405

System Design and Verification

Jason Andrews on System Level Verification - Blog
EDN names Cadence C-to-Silicon Compiler Hot Product of 2008 - Cadence Article
Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and Xilinx FPGAs - Press Release
Exploring Virtual Prototyping: Part 1 - Blog
Exploring Virtual Prototyping: Part 2 - Blog
Functional Coverage for Embedded Software - Blog
  Resources:  Product Info  |  Community  |  Events & Webinars

Logic Design

STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow - Press Release
Changes to Cadence RTL Compiler PLE Mode with 8.1 release - Blog
Expect the Unexpected - Using MSV Beyond MSV - Blog
Leveraging Silicon Virtual Prototyping Technology in Synthesis - Blog
Global Synthesis for Design Closure - White Paper
Encounter Conformal ECO Designer - Product Info
Encounter Conformal ECO Designer - Revolutionizing the Art of ECOs - Technical Paper
  Resources:  Product Info  |  Community  |  Events & Webinars

Low Power Design

Freescale Japan Adopts Cadence Low-Power Solution To Develop Advanced Power Management Chip - Press Release
Cadence Low-Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design - Press Release
Freescale Power Management Chip Tapeout - Blog
Chi-Ping Hsu Guest Blog at EDA Graffiti - Blog
Cadence and Fujitsu - Success Story
A Practical Guide to Low Power Design - eBook
Viewpoint: Low-power design brings chip, software together - EETimes
  Resources:  Solution Info  |  Events & Webinars

Digital Implementation

New Cadence Encounter Digital Implementation System Used by STMicroelectronics for 40- and 32-Nanometer Flows - Press Release
Cadence Announces Encounter Digital Implementation System with EDA Industry First End-to-End Parallel Processing Flow - Press Release
Demo and Interview: The Encounter Foundation Flow - Blog
ST Microelectronics — A Fountain-head of Design Innovations - Blog
Encounter Digital Implementation System - Datasheet
Virtuoso Digital Implementation - Datasheet
  Resources:  Product Info  |  Community  |  Events & Webinars

Visit us at SPIE!
February 22 - 27 — San Jose Convention Center, San Jose, CA — Booth #319

Lean, Engage, and Win!
Become a specialist in 5 different technology areas and win cool prizes

Custom and RF Design

Cadence Unveils Next-Generation Parallel Circuit Simulator for the Verification of Complex Analog and Mixed-Signal IC Designs - Press Release
New Multi-Mode Simulation Technologies Dramatically Boost Speed and Capacity - Cadence Article
Virtuoso MMSIM 7.1 with Accelerated Parallel Simulator - Product Info
MSIM 7.1 Enhancements Benefit RF Designers! - Blog
Noise and Jitter Analysis for PLL-Based Frequency Synthethiser Using SpectreRF - Blog
IC 6.1 Adoption guide (SourceLink account required)
  Resources:  Product Info  |  Community  |  Events & Webinars   |  Training   |  SourceLink

Archived Webinars
Webinar series 101, 201, 202, 203

New Virtuoso Support Videos (SourceLink account required)

PCB Design and IC Packaging

New Cadence Design Technology Tackles Miniaturization, Product Design and Low-Power Challenges for IC Package/SiP Designers - Press Release
Cadence Introduces Constraint-Driven High-Density-Interconnect Design Flow for PCB - Press Release
What's Good About The SPB16.2 PCB SI Release? Full Wave Field Solver! - Blog
3D IC or TSV: The Next Phase in Functional Density and Miniaturization - Blog
Correct-by-Construction Approach for HDI Designs with High-speed Interfaces - PenWell
New Allegro and OrCAD 16.2 Release Helps Companies Deal with the Latest Design Challenges - Cadence Article
  Resources:  Product Info  |  Community  |  Events & Webinars

Upcoming Allegro Webinar Series
Designing in DDRx memories with Allegro plus other exciting new webinars

Archived Webinar
Constraint-Driven HDI Design Flow


Most Popular Blog Posts
The Eternal Debate: "Like" vs. "When" Inheritance By TeamSpecman
Generation Debugging With "IntelliGen" (With Video) By TeamSpecman
Who said Cadence Can't Invent New Technology Anymore? By Esteban Svoboda
Welcome to the "Exploring the Virtual Platform" Series By Jason Andrews
What's New With Virtuoso? By Deanna Spencer
Video Chat with Lead Architect of Virtuoso Accelerated Parallel Simulator By Deanna Spencer
Levels of Logic Analysis - A Thing of the Past? What's the Trend? By Kenneth Chang
Freescale Power Management Chip Tapeout By Jack Erickson
ST Microelectronics — A Fountain-head of Design Innovations By Rahul Deokar
What's Good About The SPB16.2 PCB SI Release? Full Wave Field Solver! By Jerry Grzenia
What's Good About Differential Pair Support in Allegro PCB Editor? More Features in SPB16.2 By Jerry Grzenia
How to Simulate a Subcircuit (Netlist) With Spectre in ADE By Tawna Wilsey
MMSIM 7.1 Enhancements Benefit RF Designers! By Tawna Wilsey
3D IC or TSV: The Next Phase in Functional Density and Miniaturization By Keith Felton
CDNLive! - 10 Gbit package design paper available to conference attendees By Brad Griffin
Coffee, Anyone? By Christopher Clee
Getting Good Silicon With More Accurate Timing By Wilbur Luo
Featured Blogger
Joseph Hupcey III
Joe Hupcey III talks about Functional Verification trends, observations, new technologies and events.
Read Joe's blog

Most Popular Forum Posts
components break efforts
In System Design and Verification
Verification Plan using Eplanner
In Functional Verification
Specman Makefile generator utility In Functional Verification Shared Code
can LEC provide cdc check? In Logic Design
Refining Cell Placement at Routing Stage In Digital Implementation
ocean script: ocnPrint In Custom IC Design
Skill code for finding coordinates of selected instances in the layout In Custom IC SKILL
About Noise-Aware PLL Flow In RF Design
PCB Design with FPGA (TQFP or BGA package) In PCB Design
Convert Gerber into PDF file In PCB SKILL
.* file extensions ... In IC Packaging and SiP Design

Contact Us
We'd like to hear your comments or questions about this publication.

© 2009 Cadence Design Systems, Inc. All rights reserved.

Cadence respects your online time and privacy. To unsubscribe from all future Cadence email communications, please reply to this message and type "UNSUBSCRIBE" in the subject line.

Cadence Design Systems, Inc. | 2655 Seely Avenue | San Jose, CA 95134