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Cadence News – April 2011
New DDR4 IP Solutions Enables Differentiated SoCs and Reduces Risks

Cadence Delivers the First Commercial DDR4 IP Solution
Designing memory management IP and integrating it onto an SoC is a growing challenge that affects system performance, power, and signal integrity. But how do you incorporate higher performance memory, quickly and cost-effectively? Cadence now offers comprehensive and flexible Design IP solutions, such as for the emerging DDR4 standard, that include: hard/soft physical layer IP, controller IP, memory models, verification IP, methodologies, reference designs, and a range of design services. The solution spans every aspect of design--from silicon to package to board--freeing up your resources for product differentiation.

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What's Hot

New Unified Custom/Analog Flow
Realizing EDA360 at CDNLive! EMEA
From May 3-5, hundreds of Cadence technology users are gathering in Munich, Germany to discover fresh ideas and learn more about system-level design. The conference will also host dedicated technical sessions for Denali customers with a MemCon track, showcasing the combined strengths of the Cadence-Denali IP product portfolio.

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Visit Cadence at the TSMC Symposium

Cadence at the Heart of the Embedded Systems Conference
EDA360 and the embedded world converge at this year's Embedded Systems Conference in San Jose, May 2-5. Visit us in booth #1520 and learn more about our system-level optimization solutions.

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Spreadtrum and Cadence Collaborate EDA360 Insider: Opinions and Insights EDA360 Tech on Tour: Silicon Realization

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