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News by Design: Faster Design Closure
November 2013
Cadence at ARM TechCon

Brian Fuller
What's Around the Corner?
It’s not just about speed. Yes, we all want to get to market faster because that’s the window where the money is. But chip complexity is rising every month, and as we drop to lower nodes, accuracy becomes a great problem. And we can have speedy analysis, which is great, but that’s really only half of that problem: Even if customers can analyze, they often don't know how to fix problems. We need to deliver that as well.

That’s this month’s theme, as Cadence continues to tackle the larger closure and signoff problem with the announcement of Voltus™ IC Power Integrity Solution. Listen nearby as Anirudh Devgan walks you through the details and read Jerry Zhao’s insights into faster power integrity analysis and signoff.

A busy Fall also means new electronics innovations coming out of the annual ARM TechCon event. What will be the design consequences of the emerging Internet of Things? ARM CEO Simon Segars and HP Labs CTO Martin Fink offer amazing insight into the evolving network and how to design to it. And a fascinating panel explores the evolution of embedded software and the state of design collaboration, according to my colleague Richard Goering.

Finally, check out our special coverage of a special executive, Cadence CEO Lip-Bu Tan. He’s been involved with the company in one form or another for more than a decade, plus he has vast electronics industry experience as an investor. Check out his insights here.

Brian Fuller
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P.S. Join us Dec. 5 in San Jose at the Front-End Design Summit, our last major headquarters event of the year. In addition, we're accepting abstracts for CDNLive Silicon Valley, happening March 11-12, 2014, and for CDNLive EMEA, taking place May 19-21, 2014. Share your design experiences and insights with your peers—the Silicon Valley Call for Papers closes on Dec. 6, and for EMEA, the deadline is Dec. 12.

P.P.S. Looking for insight and diversion? Check out the latest episode of Unhinged TV, which features an interview with Samsung image-sensor designers and our infamous teardown!

    Concerns about electrostatic discharge and electromigration at advanced nodes are prompting some unusual steps. In "Paving the Way to 16/14nm", Ed Sperling, founder and editor-in-chief of Semiconductor Engineering, discusses the challenges that emerge when mixing the big picture with divide-and-conquer approaches. Read more »

Video: New Signoff Tool
Anirudh Devgan demonstrates the benefits of Voltus IC Power Integrity Solution. Watch video »

White Paper: Power Integrity
Learn how to achieve 10X faster power integrity analysis and signoff. Read paper »

Blog: Massive Parallelism
Find out how the Voltus IC Power Integrity Solution speeds analysis and signoff. Read blog »

Q&A: Interconnect IP Experts
Read this archived online chat on functional verification of SoCs. Read Q&A »

Success Story: Faraday
Faraday significantly reduces the days needed to prototype their 300M-gate design. Read story »
November 21 - December 12
China, Japan, France

November 21
Irvine, CA

November 21
Cadence San Jose Headquarters

December 5
Cadence San Jose Headquarters

December 11
Herzelia, Israel

December 11

December 12
Paris, France

For more details on all events, visit Cadence Events.


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