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News by Design: Memory
August 2013
Cadence at MemCon 2013

Taming the Memory Beast
It's not hard to forget that memory remains one of the most relentless challenges in system design. Semiconductor and EDA providers are keenly aware of this, as evidenced by a wealth of insights we received during the annual MemCon conference in Santa Clara. Mike Black from Micron talked about how Hybrid Memory Cube technology can help us scale the memory wall; Bob Brennan from Samsung gave a sneak peek at new memory architectures. Martin Lund from Cadence reassured us that memory innovation will keep up with our productivity expectations and a lively panel laid out the challenges of memory design in the coming years.

At the same time, Cadence announced new memory models for five emerging standards. If you're looking for more insight, don't miss Sumeet Agarwal's recent post on verification IP. What else is new this summer? Our 25th anniversary, that's what! Richard Goering and I have already written about the "dazzling decade" of EDA innovation milestones and what the next 25 years will bring. And there's a lot more in store as we celebrate industry innovation for a full year.

Thanks for reading.

P.S. Miss MemCon? Not really. Check out the proceedings, watch the recap video and see what was going on by visiting our Flickr page.

Connect and Share with Cadence

    At the ChipEstimate.TV station at MemCon, Sean O'Kane shares a laugh with Andrew Hampy.

For an overview of what happened at MemCon, check out O'Kane's interview with Richard Goering and Brian Fuller.

Saving 2 months of debug time — read how
Samsung's Bob Brennan: Maximizing Memory Efficiency
LPDDR3 or Wide I/O? View webinar for answers
Blog: Wide I/O 2, HMC Advance 3D-IC Standards
Cadence has announced the industry's first memory models for five emerging standards: Wide I/O 2, Hybrid Memory Cube (HMC), LPDDR4, eMMC 5.0, and LRDIMM. Richard Goering explains why this is important.
Read all blogs »

Blog: Overcoming Memory Challenges
Electronics apps, especially mobile, are causing architectural fragmentation in the semiconductor memory industry, said Cadence's Martin Lund at MemCon 2013. Brian Fuller covers Lund's keynote.
Read all blogs »

White Paper: Power-Aware Challenges of Memory Interface Designs
Learn how modern tools can address power-aware signal integrity challenges related to I/O modeling, interconnect modeling, simulation, and analysis.
Read paper »

Article: 5 Emerging DRAM Interfaces
Understand the bandwidth, power, and area advantages and tradeoffs of LPDDR3, LPDDR4, HMC, Wide I/O 2, and High Bandwidth Memory (HBM). Read article »
CDNLive Beijing
September 10
Learn about new technologies, chat with our tech experts, share best practices, and network with our peers at our popular user conference. Get details »

CDNLive Shanghai
September 12
Learn about new technologies, chat with our tech experts, share best practices, and network with our peers at our popular user conference. Get details »

Live Online Chat with Memory IP Experts
September 17
Ask questions and get immediate answers from our panel of memory IP experts during our hour-long online session. Get details »

PCB West 2013
September 24-26
Meet with us at Booth #406 at the Santa Clara Convention Center, and learn more about our OrCAD®, Allegro®, and Sigrity™ technologies. Get details »

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