Customer Newsletter - May 2013

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Meet with Cadence at DAC 2013


Register now for Cadence® technical sessions and breakfast and lunch seminars at DAC 2013 in Austin, Texas. We’re offering a full schedule of opportunities for you to enhance your skills, share ideas to solve tough design challenges, and network with your peers. Sign up today to reserve your spot for sessions and seminars designed to help you realize the highest quality system-on-chip devices and complete systems.


Cadence to Acquire IP Business of Evatronix

Find out how Cadence is further expanding our IP portfolio with our intent to acquire the IP business of Evatronix SA SKA. With a broad base of approximately 600 customers, Evatronix is an established provider of USB, MIPI, display, and storage controller IP.

Blog: Parallelized Computation and STA

Richard Goering discusses how the new Cadence Tempus™ Timing Signoff Solution performs parallelized computation efficiently to help speed up static timing analysis.

Submit Your Papers for CDNLive Boston

Papers are at the core of CDNLive Boston, taking place Aug. 27. Submit your abstracts by 5pm on June 7 for consideration.
Get details
Enhance Low-Power Verification Productivity

Learn how the new Cadence® Incisive® Enterprise Simulator 13.1 improves low-power verification productivity by 30%, enabling more thorough verification for complex systems on chip (SoCs).
Learn more
Achieve Superior PPA at 20nm and Below

The new release of Cadence Encounter® Digital Implementation System provides full production silicon-proven capabilities and readiness for 20nm design, with support for early adopters of 14nm and 16nm FinFET process technologies.
Learn more

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