Customer Newsletter - January 2013

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Cadence DRAM IP Paper Wins TSMC Customers' Choice Award


For the second year in a row, Cadence received the prestigious "Customers' Choice Award" at TSMC's recent Open Innovation Platform Ecosystem Forum. The award was for a paper on DRAM IP that focused on current and emerging trends in high-speed memory interfaces and the design IP required to enable them.

Find out how you can quickly adopt the latest high-speed memory interfaces in sub-28nm designs by reading this award-winning paper.


Introducing Virtuoso Advanced Node for Design Success at 20nm and Below

To address the design and manufacturing complexities inherent in smaller geometries, Cadence has introduced Virtuoso® Advanced Node, a new set of custom/analog capabilities for designing at 20nm and below.

This new specification-to-signoff methodology increases overall verification productivity by up to 30 percent. Leading companies have embraced this methodology and are benefitting from greater efficiency and predictability with their 20nm projects.

Blog: Cadence, ARM, and Samsung Collaborate to Develop 14nm FinFET Test Chip

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node.

Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully completed in about eight weeks. This is the first 14nm tapeout to use the high-performance ARM Cortex-A7 processor core.

Texas Instruments Achieves 96% Accuracy

Palladium XP and Encounter Power System enable success
Feature story
Registration Now Open, CDNLive Silicon Valley

Join us in Santa Clara, March 12-13
Learn more
Encounter Turbo-Charges 28nm Design at Avago

New GigaOpt technology boosts performance by 57%
Read press release

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