Customer Newsletter - June 2012

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Xilinx Slashes Verification Time Using Incisive Specman/e Solution

To accelerate its development cycle, Xilinx uses Cadence Incisive Enterprise Simulator with Specman macros for swift IP design testing.

In addition to runtime improvements that save Xilinx 20% to 30% in simulation time, the Specman macro solution is flexible, easy to use, and effectively free as all Enterprise Simulator licenses include a Specman license.

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GLOBALFOUNDRIES and Cadence collaborate on DRC+ technology

To guarantee high yield and manufacturability at advanced process nodes, GLOBALFOUNDRIES needed to go beyond traditional design-rule checking (DRC) and develop a new set of incremental design-for-manufacturing (DFM) verification methodologies.

GLOBALFOUNDRIES collaborated with Cadence to pioneer pattern matching-based DRC+ technology, driving faster turnaround times and first-pass-correct silicon.

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Blog: DAC Panelists Discuss Success at 28nm and Below

A panel of experts at a Cadence-sponsored Design Automation Conference (DAC) panel provided fresh insights into what it takes to achieve silicon success at 28nm, 20nm and beyond.

Learn how speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and technology challenges and solutions.

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Archived Webinars: Industry Leaders Unveil Shared Vision for 20nm

Gain Clarity to Succeed at Advanced Nodes
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PCI-SIG Developers Conference, Santa Clara

Chat with Cadence IP/VIP experts in PCI Express at booth 1
Event details

SiliconBlue Technologies Achieves First-Pass Silicon Success

Leverages Cadence TSMC-certified DFM Services
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