Customer Newsletter - February 2012

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Allegro and OrCAD User Papers, Roadmaps and Techtorials at CDNLive! Silicon Valley

CDNLive Silicon Valley is just around the corner. This year, we have extended CDNLive! with a free one-day event specifically for PCB and IC packaging designers.

Join us March 15 on the Cadence campus to meet with our experts on Allegro/OrCAD technology. Don’t miss out—register for both CDNLive and our on-campus event today!

Full details


Cadence and Samsung Foundry Collaborate to Deliver DFM Solution

Cadence and Samsung Electronics’ Foundry business, Samsung Foundry, have collaborated and developed “in-design” and signoff DFM flows to tackle physical signoff and electrical variability optimization.

The new flows provide customers with a proven foundry option for advanced-node designs built on the Cadence digital and custom/analog implementation technologies.

Learn more

Best Practices for Selecting and Using Verification IP

While commercial verification IP (VIP) can save considerable time and engineering resources, there are several decisions you need to make in order to optimize the value you receive.

Should you buy VIP or build your own, what should you consider in selecting VIP, and how can you make best use of it once you have it?

Read blog
View VIP Catalog

Cadence Tutorials and Papers at DVCon in San Jose

Cadence solutions address your toughest functional verification challenges
Get more information

Hear Cadence Expert Osman Javed at Ethernet Summit

See our demo and learn about the latest advances in Ethernet technology
Event details

Cadence Nominated for Four ACE Awards

Cast your vote for the best of the best in today’s electronics industry
Vote now


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