Customer Newsletter - November 2011

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ARM and Cadence Achieve Industry Milestone

ARM and Cadence recently announced the tape out of the industry’s first 20nm design based on the ARM Cortex™-A15 MPCore™ processor. The test chip, targeting TSMC’s 20nm process, was jointly developed by engineers from ARM, Cadence and TSMC using a Cadence RTL-to-signoff flow.

This milestone announcement is the result of an 18 month collaboration between ARM and Cadence on optimized design flows for the Cortex-A15 processor. The companies also recently signed a multi-year technology agreement that will provide ARM engineering teams with ongoing access to Cadence products.


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CDNLive Silicon Valley Call for Papers Extended

Act now to submit an abstract for inclusion in our eighth annual user conference, CDNLive! Silicon Valley, being held in San Jose, March 13-14, 2012. All Cadence® technology users including IC and PCB designers, system architects, verification, CAD engineers, SoC/IP integrators, and project managers are invited to submit abstracts on design topics, techniques and methodologies.

Following this year’s theme—Connect. Share. Inspire.—we encourage you to share your experience and expertise with your peers in the semiconductor design community. The abstract submission deadline has been extended to December 2, 2011.


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Xilinx and Cadence Introduce an Extensible Virtual Platform

Xilinx and Cadence announced that they have teamed to develop the industry’s first virtual platform to enable system design, software development, and testing of Xilinx Zynq™-7000 Extensible Processing Platform (EPP)-based systems in advance of hardware availability.

This solution further enhances the development environment for Xilinx’s ARM® processor-based processing platform and speeds the development flow for embedded designers, enabling software to drive hardware design.


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Technology on Tour Available On Demand, 24/7

Learn the latest technologies, and chat live with experts
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TSMC Reference Flow 12 Shortens Time to Market

Based on a new design methodology developed by Cadence
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QLogic Utilizes Palladium XP to Reduce Design Time

System-level verification ensures success of complex switch design
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