Cadence News - August 2011

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20nm Design - Challenges and Opportunities

Are you designing at 20nm technology today, or planning to in the near future? Download our white paper that outlines 20nm design challenges and learn how this advanced technology node will transform SoCs and EDA.

Get the details on manufacturing issues specific to 20nm that pose a challenge when developing high-quality silicon and SoC. Learn the latest techniques and methodologies that will put you on the most practical and predictable path to 20nm silicon.

Get the white paper now!


IBM Shortens SOI Model Validation Cycle Using Virtuoso

Compact models must undergo a stringent qualification process before they are released to customers--and customers can’t afford to wait very long. IBM recently initiated a verification effort with Cadence to generate a robust, exhaustive, and efficient model qualification flow using the Virtuoso Spectre Circuit Simulator for IBM SOI processes at advanced nodes.

Find out how Cadence helped IBM reduce the overall SOI model validation cycle time for new compact model code by 30 percent.

Learn more

Sunplus Speeds Design and Verification Time

Sunplus Technology, a leading multimedia IC design company, adopted the Cadence® transaction-level modeling (TLM) flow with Cadence C-to-Silicon Compiler for its next-generation multimedia system-on-chip (SoC) design.

The Cadence TLM approach helps Sunplus boost design team productivity and control development costs while ensuring high-quality chips for their TV, set-top box, and DVD offerings.

Full story

Cadence and ARM Fireside Chat  

See the latest in our collaboration at the 2011 Technical Conference

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CDNLive! Israel  
Cadence VIP Technical Seminar

Join us for an in-depth look at the Cadence Verification IP Catalog

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Customer Success  
Intel Developers Forum

Explore Cadence solutions to realize innovative products based on Intel technology

Event details


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