San Jose, CA. 22 Jun 2011
Cadence Demonstrates PCI Express 3.0 Offering at 2011 PCI-SIG Developers Conference
Cadence Design Systems, (NASDAQ: CDNS), a leader in global electronic design innovation, showcases its integration-ready, proven PCI® Express 3.0 solutions at the 2011 PCI-SIG® Developers Conference.
Cadence demonstrates design and verification IP that supports v1.0 of the PCI Express 3.0 specification. With more than 10 designs taped-out using its PCI Express 3.0 IP and more than 50 designs verified with its PCI Express 3.0 VIP, Cadence highlights how customers can rapidly design and verify ASIC or SoC devices for emerging PCI Express 3.0 applications like storage, supercomputing, enterprise and networking. The company will highlight its PCI Express 3.0 controller IP, as well as verification IP and design-in kits for package-to-board implementation.
Design IP Demonstration:
Cadence is demonstrating a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration implemented in silicon on an advanced-node PMC-Sierra ASIC. The Cadence PCI Express 3.0 controller is integrated in an ASIC on a reference card which connects to a PCI Express Gen3 backplane exerciser and a PCI Express Gen3 logic analyzer to demonstrate PCI Express 3.0 traffic running at 8 GT/s per lane. Complying with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification, the Cadence PCI Express 3.0 design IP has been successfully implemented in silicon with advanced capabilities like Single-Root I/O Virtualization (SR-IOV) and the latest engineering change notices (ECNs) such as ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.
Verification IP Demonstration:
Cadence will also demonstrate its PCI Express 3.0 VIP solution. The demonstration will show the unique Compliance Management System (CMS) for the PCI Express protocol which provides interactive, graphical analysis of coverage results correlated directly to the protocol specification, and PureSuite which provides thousands of test cases to simulate PCI Express traffic and check for compliance with the PCI Express specifications.
June 22-23, 2011
Wednesday, June 22, 11:30 a.m. – 1 p.m., 3 – 3:30 p.m. and 5:30 – 7 p.m.
Thursday, June 23, 10-10:30 a.m., 12:30-1:30 p.m.
Cadence PCI-SIG Booth #15
Santa Clara Convention Center, Santa Clara, CA
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com