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EDA(Electronics Design Automation)분야의 세계 최대 마켓리더인 케이던스(Cadence Design Systems Inc.)는 전세계 반도체, 통신장비, 멀티미디어 및 가전제품 회사들이 다양한 제품을 적기에 개발하고 생산할 수 있도록 EDA 소프트웨어와 디자인 서비스를 제공하고 있습니다. 미국 캘리포니아주 산호세에 본사를 두고 있으며, 세계 주요지역에 현지법인, 연구소, 디자인센터를 두고 있습니다. 회사소개(About Cadence Korea).



Cadence News

2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009

June
22 Jun 2016: Cadence Debuts PSpice Web Portal and Ecosystem to Help Designers Address System Level Mixed-Signal Wireless and IoT Challenges 07 Jun 2016: Cadence and SMIC Collaborate on Delivery of Low-Power 28nm Digital Design Reference Flow06 Jun 2016: Cadence Expands Collaboration with ARM to Accelerate Custom SoC and IoT System Designs with Industry’s First End-to-End Hosted Design Solution05 Jun 2016: ChipEstimate.com Launches New Site with Extended Availability of Semiconductor IP Resources03 Jun 2016: Cadence Corporate Vice President - Finance Sean Sobers to Present at the Nasdaq 34th Investor Program 02 Jun 2016: Hitachi Adopts Cadence AMS Model-Based Methodology and Tools for Mixed-Signal Design Verification 01 Jun 2016: Cadence Next-Generation Virtuoso Platform Deployed by STMicroelectronics for SmartPower Technologies
May
31 May 2016: Media Alert: Cadence to Showcase System Design Enablement Innovations at DAC 201631 May 2016: Media Alert: Meet Leading IP Suppliers and Foundries at DAC 2016 During ChipEstimate.com IP Talks!29 May 2016: Cadence Delivers Rapid Adoption Kits Based on a 10nm Reference Flow for New ARM Cortex-A73 CPU and ARM Mali-G71 GPU16 May 2016: Uurmi Fog Removal Software Now Available on Cadence Tensilica Vision DSPs12 May 2016: Cadence Corporate Vice President - Finance Sean Sobers to Present at the Baird Global Consumer, Technology and Services Conference 10 May 2016: Cypress Adopts Cadence Digital Implementation and Circuit Simulation Tools for 40nm Automotive Designs09 May 2016: Tezzaron Cuts Design Time in Half with Cadence Full-Flow Digital RTL-to-Signoff Solution 04 May 2016: Faraday Reduces Packaging Design Time by 60 Percent Using Cadence OrbitIO Interconnect Designer and SiP Layout03 May 2016: New Cadence Allegro Platform Accelerates Design of Compact, High-Performance Products Using Flex and Rigid-Flex Technologies03 May 2016: Cadence Expands OrCAD Solution to Address Flex and Rigid-Flex Design Challenges for IoT, Wearables and Mobile Devices 02 May 2016: Cadence Announces New Tensilica Vision P6 DSP Targeting Embedded Neural Network Applications
April
28 Apr 2016: Cadence Completes Acquisition of Rocketick Technologies27 Apr 2016: Cadence Named One of FORTUNE Magazine’s 50 Best Workplaces for Giving Back25 Apr 2016: Toshiba Adopts Cadence Innovus Implementation System for Production Mobile Memory Controller Design25 Apr 2016: Cadence Reports First Quarter 2016 Financial Results25 Apr 2016: Cadence Chief Financial Officer Geoff Ribar to Retire in March 201718 Apr 2016: Media Alert: Connect, Share, and Inspire at CDNLive EMEA 2016—Cadence User Conference14 Apr 2016: Cadence Corporate Vice President - Finance James Haddad to Present at the Jefferies Technology, Media & Telecom Conference 13 Apr 2016: UMC Qualifies Cadence Virtuoso LDE Analyzer for its 28HPC<sup>U</sup> Process11 Apr 2016: Cadence to Acquire Rocketick, Delivering Revolutionary Parallel Logic Simulation Speed-up08 Apr 2016: Cadence Announces First Quarter 2016 Financial Results Webcast 07 Apr 2016: Cadence and University of Oxford Foster the Advancement of Formal Verification Innovation 05 Apr 2016: Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
March
30 Mar 2016: Cadence Digital and Signoff Tools Certified on Samsung Foundry’s 14LPP Process22 Mar 2016: Ethertronics Reduces Design Schedule by Half and Achieves More than 60 Percent Mask Cost Savings Using Cadence Conformal ECO Designer16 Mar 2016: New MEMS Design Contest Encourages Advances in MEMS Technology15 Mar 2016: Cadence and TSMC Expand Collaboration Efforts on Integrated Design Flow for InFO Technology 15 Mar 2016: Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production 15 Mar 2016: Cadence Design IP to Support TSMC 16FFC and 28HPC+ Process Technologies14 Mar 2016: Cadence Announces Availability of Complete IC Packaging Design and Analysis Solutions for Advanced Fan-Out Wafer-Level Chip Scale Packaging14 Mar 2016: Mellanox and Cadence Demonstrate PCI Express® 4.0 Multi-Lane PHY IP Interoperability 14 Mar 2016: Cadence Announces DDR4 and LPDDR4 IP Achieve 3200 Mbps on TSMC 16nm FinFET Plus Process08 Mar 2016: Media Alert: Cadence to Showcase Design Solutions at TSMC’s 2016 Technology Symposium03 Mar 2016: Cadence Named to FORTUNE’s 2016 List of “100 Best Companies to Work For”
Feburary
29 Feb 2016: Hiroshima University Research Team Accelerates Automotive Algorithm Development with Cadence Protium Rapid Prototyping Platform 24 Feb 2016: Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow 23 Feb 2016: Realtek Licenses Cadence Tensilica Fusion DSP to Support Ultra-Low-Power Always-On Functions in the RTS3110/RTS3111 Context Hub Chip 22 Feb 2016: Cadence Announces the HiFi Integrator Studio 22 Feb 2016: Spreadtrum Licenses Tensilica HiFi Audio/Voice DSP 18 Feb 2016: Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon 201616 Feb 2016: Cadence OrCAD Capture Delivers Support of Intel Schematic Connectivity Format for Automated Design Reviews 16 Feb 2016: Cadence Innovus Implementation System Qualified on Samsung 10nm FinFET Process10 Feb 2016: Cadence President and Chief Executive Officer Lip-Bu Tan to Present at the Morgan Stanley Technology, Media & Telecom Conference 08 Feb 2016: Building the Car of the Future Today—Cadence Showcases Automotive Solutions at embedded world 201608 Feb 2016: Media Alert: Cadence to Showcase Tensilica DSPs and Design IP at Mobile World Congress 201603 Feb 2016: Cadence Reports Fourth Quarter and Fiscal Year 2015 Financial Results02 Feb 2016: New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time 02 Feb 2016: Media Alert: Cadence to Host Embedded Neural Network Summit01 Feb 2016: Cadence Announces Complete Digital and Signoff Reference Flow for Imagination Technologies’ PowerVR Series7 GPUs
January
26 Jan 2016: Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process26 Jan 2016: Media Alert: Qi Wang to Keynote Asia and South Pacific Design Automation Conference 201620 Jan 2016: Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces18 Jan 2016: HiSilicon Adopts Cadence Innovus Implementation System for Production DSP Designs13 Jan 2016: Media Alert: Cadence to Showcase Signal Integrity Solutions for System-Level, Power-Aware Multi-Gigabit Interface Compliance at DesignCon 201613 Jan 2016: Arrow Electronics and Cadence Collaborate to Accelerate the Development of Production-Ready Products for Hardware Engineers11 Jan 2016: Cadence Tempus Timing Signoff Solution Surpasses 200 Tapeout Milestone Within Two Years of Product Inception08 Jan 2016: Cadence Announces Fourth Quarter and Fiscal Year 2015 Financial Results Webcast 06 Jan 2016: Cadence Tensilica HiFi Audio DSP Becomes First IP Core Approved for Dolby MS12 Multistream Decoder05 Jan 2016: DSP Concepts Enhances Audio Weaver to Support Cadence Tensilica HiFi DSPs 04 Jan 2016: dbx-tv Total Technology Now Available on Cadence Tensilica HiFi Audio/Voice Processors
 
케이던스 코리아(유)
경기도 성남시 분당구
금곡동 196. 한전기공빌딩 6층
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