This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog® hardware description language (HDL), discusses the benefits of the new features, and demonstrates how design and verification can be more efficient and effective when using SystemVerilog constructs.
The course consists of three modules:
- The SystemVerilog for Design module examines RTL design convenience and synthesis features.
- The SystemVerilog for Verification module explores verification features such as classes, constrained random stimulus, and coverage.
- The SystemVerilog Assertions module provides an in-depth introduction to SystemVerilog Assertions with guidelines to help you create, manage and debug assertions for complex design properties.
This five-day class is an intensive concentration of content that was previously offered as separate courses totaling seven days of training. The instructor will tailor the class presentation to fit the topics of interest into just five days. Students will take with them for reference purposes the full seven days of material.
After completing this course you will be able to:
- Understand and use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators; relaxation of Verilog language rules; fixes for synthesis issues; enhancements to tasks and functions; new hierarchy and connectivity features, and interfaces.
- Appreciate and apply the SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for more effective and efficient verification.
- Understand how to use SystemVerilog Assertions (SVA) for self-checking code. Define effective assertions from simple, instantaneous Boolean checks to complex multi-cycle assertions incorporating repetition, over-lapping, concurrency and alternate behavior.
Software Used in This Course
- Incisive Enterprise Simulator XL
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
SystemVerilog for Design
- SystemVerilog Overview
- Standard Data Types and Literals
- Procedures and Procedural Statements
- User-Defined Data Types
- Hierarchy and Connectivity
- Tasks and Functions
- Conclusions and Next Steps
SystemVerilog for Verification
- Verification Overview
- Verification Blocks
- Transaction-Level Modeling
- SystemVerilog Classes
- Random Stimulus
- Class-Based Randomization
- Functional coverage
- Queues and Dynamic Arrays
- Interprocess Synchronization
- Direct Programming Interface (DPI)
- Introduction to SystemVerilog Assertions
- Conclusions and Next Steps
- Design engineers
- Verification engineers
You must have:
- The ability to navigate a file system and use a text editor
- A basic understanding of digital hardware design and verification
- A working knowledge of the Verilog HDL
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