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Course TitleAllegro GRE Interconnect Flow Planning v16.5
Course CategorySystem Interconnect Design – Allegro & OrCAD
Duration1 day
Product Versionv16.5

Course Description

The Global Route Environment (GRE) provides the technology and methodology to capture as well as adhere to a designer’s intent. In the Allegro® GRE Interconnect Flow Planning course, you apply this technology and methodology to convert your design intent into the final board design.

You develop the first stage of flow planning by creating bundles manually, applying constraints to them, and editing the bundles. After this initial stage, you develop and define the flow of the bundles. After defining the flow, you plan (or route) it. You explore the three phases of planning, spatial, topological, and accurate, in detail.

Learning Objectives

After completing this course, you will be able to:

o   Understand GRE terminology and technology

o   Create, edit, and use bundles

o   Create and modify the flow of a bundle

o   Understand the entire planning process

o   Identify the three stages of planning, spatial, topological, and accurate

o   Have multiple designers work on the same design at the same time.

Software Used in This Course

o   Allegro PCB Designer product license with the GRE-Full Router product option.

Software Release(s)

o   SPB 16.5

Course Agenda

Note that this course can be tailored to better meet your needscontact the Cadence training staff for specifics.


o   Introduction to the Interconnect Flow Designer (IFD) and GRE

o   Creating and Using Bundles

o   Editing Bundles

o   Flow Editing

o   Planning Overview

o   Spatial Planning

o   Topological and Accurate Planning

o   Increasing Throughput

Flow Editing


o   PCB Designers


You must have experience with or knowledge of the following software:

o   Allegro PCB Editor

케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
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