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Course TitleEDI Advanced Implementation_11.1
Course CategoryDigital IC Design – Encounter
Duration5 Days
Product Versionv11.1

Advanced Encounter Digital Implementation (Hierarchical, Low Power, CCOpt, dbtcl and FlexModel) v11.1


Course Description

In this course, you explore hierarchical design implementation by using the Encounter® Digital Implementation software. You learn several techniques for implementing hierarchical designs, low power design, clock concurrent optimization and hierarchical timing closure strategies, prototyping flow.


Learning Objectives

After completing this course, you will be able to:

  • Do partitioning with hierarchical design
  • Do bus planning
  • Implement with ILMs
  • Do timing closure with hierarchical design
  • Implement CPF-based low power design with EDI
  • Do clock concurrent optimization
  • Run foundation flow scripts
  • Do prototyping flow with FlexModel

Software Used in This Course

  • Encounter Digital Implementation System XL

Software Release(s)

  • EDI111

Course Agenda

Note that this course can be tailored to better meet your needs contact the Cadence training staff for specifics.


Day 1  (Hierarchical Design Flow)

  • EDI Overview
  • Partition the Design
  • Bus Planning
  • Interface Logic Models (ILMs)
  • Automatic Floorplan Synthesis (AFS)
  • Post Assembly Closure Flow
  • Foundation Flow Scripts
  • LAB  

Day 2 - 3 (Low Power Implementation with EDI)

  • Low Power Introduction
  • Power Reduction
  • Common Power Format
  • Checking a Low-Power Design Encounter Conformal Software
  • Multiple Supply Voltage and Power Shutoff Synthesis
  • Reducing Dynamic Power during Synthesis
  • Optimizing for Leakage Power in Synthesis
  • Implementing Low-Power Using EDI Technology
  • MMMC Settings through CPF Flow
  • Creating Physical Power Domain
  • Level-Shifter and Isolation Cells
  • Substrate Biasing
  • Power Shutoff Domain Implementation
  • Power Planning and Power Routing
  • Power Analysis and Reporting
  • Power Optimization during Placement, CTS, and Timing Optimization
  • Leakage Power Optimization
  • Power-Domain-Aware routing
  • Low-Power Foundation Flow
  • Signoff Considerations for Low-Power Designs
  • LAB

Day 4 (CCOpt and dbtcl)

  • What is CCOpt
  • CCOpt Integration with EDI11
  • Logic Chains
  • CCOpt Phases of Operation
  • CCOpt Commands
  • LAB
  • Database Access with DBTCL (dbGet, et al.)
  • LAB

Day 5 (Prototyping flow with FlexModel)

  • Prototyping Foundation Flow for Flat
  • Prototyping Features
  • Explorationm & Planning – Flow overview
  • Exploration & Planning – Generate Models
  • Exploration & Planning – Debug Constraints and Plan Design
  • Exploration & Planning – Analyze Floorplan and Adjust
  • Exploration & Planning – Define Partition
  • Exploration & Planning – Finish and Save partitions
  • LAB


  • CAD Engineers
  • Chip Designers
  • Physical Layout Designers  


You must have experience with or knowledge of:

  • Design methodology
  • Place and Route
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
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