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Course TitleConformal Equivalence Check & Conformal ECO_11.1
Course CategoryDigital IC Design – Encounter
Duration3 Days
Product Version11.1

Logic Equivalence Checking & ECO with Encounter Conformal


Course Description

In this course, you use the Encounter® Conformal® Equivalence Checker to perform functional verification. You learn the basic flow of equivalence checking and how to run hierarchical comparison of designs. The lab exercises follow major topics and are designed to be directly applicable in design and design verification. After completing this course, you will be able to set up and verify your designs, analyze the results, and debug failing results.  Also Cadence® Encounter® Conformal® ECO Designer combines logic equivalence checking (for the most complex SoC and datapath-intensive designs) with functional ECO analysis and generation, design netlist modification, clock domain synchronization, and semantics checks. With a complete ECO solution that spans different parts of the RTL-to-GDSII flow, design teams benefit from automation, predictability, and the highest quality ECOs. This course provides an in-depth look at the software along with hands-on experience required to use the tool.

Learning Objectives

In this course, you will

  • Use Encounter Conformal logic equivalence checking for flat and hierarchical design comparison
  • Read libraries and designs
  • Apply design constraints and modeling directives
  • Debug mapping
  • Analyze and fix nonequivalences
  • Analyze and fix aborts
  • Use Encounter® Conformal® Engineering Change Order (ECO) for flat and hierarchical design
  • Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology.
  • Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
  • Run a postmask ECO using Conformal® ECO GXL
  • Learn the many options and capabilities of Conformal® ECO

Software Used in This Course

  • Encounter RTL Compiler
  • Encounter Conformal ECO Designer
  • Encounter Conformal ECO Designer GXL
  • Encounter® Conformal® Equivalence Checker XL

Software Release(s)

  • CONFRML111, RC111

Course Agenda

Day 1

  • Introduction to the Encounter Conformal product family
  • Introduction to logic equivalence checking
  • LEC flow - Setup mode
  • LEC flow - LEC mode
  • Hierarchical comparison of designs

Day 2

  • Debugging Setup Issues
  • Debugging Mapping Issues
  • Debugging Nonequivalences
  • Debugging Aborts

Day 3

  • Encounter Conformal Product Introduction
  • ECO Challenges
  • Front-end Functional ECO
  • Hierarchical ECO
  • Physically Aware ECO
  • ECO Variations


  • Logic Designers
  • Place and Route Designers
  • Verification Engineers
  • Custom Circuit Designers
  • Engineering Managers
  • Memory Designers
  • Verification Engineers
케이던스 코리아(유)
경기도 성남시 분당구 판교로 344
엠텍IT타워 9층/2층(교육장)
(구. 삼평동 688-1)
전화번호: 031-728-3111(代)
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