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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
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        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
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      • AI IP Portfolio
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      • INDUSTRIES
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        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
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Custom IC / Analog / RF Design

Analog Modeling with Verilog-A

Behavioral Modeling with Verilog-AMS

Mixed Signal Simulations Using Spectre AMS Designer

Pegasus Verification System

Physical Verification System

Quantus Transistor-Level T1: Overview and Technology Setup

Quantus Transistor-Level T2: Parasitic Extraction

Quantus Transistor-Level T3: Extracted View Flows and Advanced Features

SKILL Development of Parameterized Cells

SKILL Language Programming

SKILL Language Programming Introduction

Spectre Accelerated Parallel Simulator

Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs

Spectre Simulator Fundamentals S1: Spectre Basics

Spectre Simulator Fundamentals S2: Large-Signal Analyses

Spectre Simulator Fundamentals S3: Small-Signal Analyses

Spectre Simulator Fundamentals S4: Measurement Description Language

Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis

Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis

Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners

Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans

Virtuoso ADE Verifier S1: Setup, Run and View Verification Results

Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant

Virtuoso Connectivity-Driven Layout Transition

Virtuoso Layout Design Basics

Virtuoso Layout for Advanced Nodes and Methodology Platform

Virtuoso Layout for Advanced Nodes: T1 Place and Route

Virtuoso Layout for Advanced Nodes: T2 Electromigration

Virtuoso Layout Pro: T1 Environment and Basic Commands (L)

Virtuoso Layout Pro: T2 Create and Edit Commands (L)

Virtuoso Layout Pro: T3 Basic Commands (XL)

Virtuoso Layout Pro: T4 Advanced Commands (XL)

Virtuoso Layout Pro: T5 Interactive Routing (XL)

Virtuoso Layout Pro: T9 Virtuoso Design Planner

Virtuoso Schematic Editor

Virtuoso Space-based Router

Virtuoso Space-Based Router Express

Virtuoso Spectre Pro S1: DC Algorithm

Virtuoso Visualization and Analysis

Digital Design and Signoff

Advanced Synthesis with Genus Stylus Common UI

Basic Static Timing Analysis

Conformal Equivalence Checking

Fundamentals of IEEE 1801 Low-Power Specification Format

Genus Synthesis Solution With Stylus Common UI

Innovus Block Implementation with Stylus Common UI

Innovus Hierarchical Implementation with Stylus Common UI

Innovus Implementation System (Block)

Innovus Implementation System (Hierarchical)

Joules Power Calculator

Low-Power Synthesis Flow with Genus Stylus Common UI

Tempus Signoff Timing Analysis and Closure

Tempus Signoff Timing Analysis and Closure with Stylus Common UI

Test Synthesis with Genus Stylus Common UI

Voltus Power Grid Analysis and Signoff with Stylus Common UI

Voltus Power-Grid Analysis and Signoff

PCB and Package Design

Allegro Design Entry HDL Front-to-Back Flow

Allegro High-Speed Constraint Management

Allegro PCB Editor Basic Techniques

Allegro PCB Editor Intermediate Techniques

Allegro PCB Editor SKILL Programming Language

Allegro PCB Librarian

Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM

Sigrity PowerDC and OptimizePI

SiP Layout

System Design and Verification

C++ Language Fundamentals for Design and Verification

Low-Power Simulation with IEEE Std 1801 UPF

Metric Driven Verification using Cadence vManager

Perspec System Verifier - Basic

Specman Fundamentals for Block-Level Environment Developers

SVA, Formal and JasperGold Fundamentals for Designers

SystemC Language Fundamentals

SystemVerilog Accelerated Verification with UVM

SystemVerilog Assertions

SystemVerilog for Design and Verification

Verilog Language and Application

Xcelium Integrated Coverage

Xcelium Simulator

Tensilica Processor IP

Tensilica Xtensa NX Processor Fundamentals

Tensilica Xtensa LX Processor Fundamentals


 

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