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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
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        • Hyperscale Computing
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        • Automotive
        • Hyperscale Computing
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  • Virtuoso Layout Pro (Virtuoso_XL & GXL): T3 , T4 , T5



Virtuoso Layout Pro (Virtuoso_XL & GXL): T3 , T4 , T5

Instructor-Led Schedule
날짜 버전 국가 위치
Scheduled upon demandOn demand EnrollINQUIRE

Length : 2 days

Course Description

This course focuses on the basic concepts required to work with Virtuoso® Layout Suite XL to create a layout using a connectivity-driven flow. After that, you analyze how to generate clones as free objects, grouped objects, and synchronized family. Also you explore techniques to increase your productivity using all the assisted features in the Create Wire family of commands in Virtuoso® Layout Suite XL.

View the videos available in the course in the links given below:

Generating Clones as Free Objects

Generating Clones as Grouped Objects

Generating Clones as Synchronized Family

Generating Synchronous Copy of Wires

Generating Clones From Modgen

Creating Mutant Clones

Updating the Net and Pin Names – Overview

Learning Objectives

After completing this course, you will be able to:

  • Use VLS-XL to create a new layout cell from scratch
  • Debug and address connectivity errors in your layout design
  • Analyze how the Layout-XL binder and extractor work
  • Describe how Constraint Groups affect your layout work. Create your layout structures using Generate Clones and Create Synchronous Copy features
  • Update your layout after an Engineering Change Order (ECO)
  • Use the Design-Rule-Driven (DRD) Editing and the DRD Interactive Compactor features Analyze the basic concepts and settings in wire creation
  • Create and modify the wires
  • Explore the assisted wires creation
  • Use the smart auto via feature (Optional Appendix)

Software Used in This Course

  • Virtuoso Layout Suite XL

Software Release(s)

  • MMSIM15.1 and IC 6.1.7

Course Agenda

Day 1

  • Design Creation and Placement
  • Binder and Extractor
  • Using Constraint Groups in Virtuoso Generating Clones
  • Updating Connectivity and Nets
  • Design-Rule-Driven Editing

Day 2

  • Basic Concepts and Settings in Wire Creation
  • Creating and Modifying Wires
  • Assisted Wires Creation
  • Smart Auto Via (Optional Appendix)

Audience

  • Layout Design Engineers
  • Layout CAD Managers

Prerequisites

  • Experience with layout design
  • Knowledge of schematic symbols and MOS devices
  • Basic knowledge of Unix/Linux

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

Course ID: 85092

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