This course covers Modeling, Simulation and Analysis of Power-Aware Parallel Bus System (DDR3 and DDR4) using the Allegro Sigrity SystemSI - PBA II.
After completing this course, you will be able to:
- Build a block-level topologies of simple DDR3 and DDR4 parallel bus system (DDR3-SPBS and DDR4-SPBS) and power aware parallel bus systems (DDR3-PAPBS and DDR4-PAPBS) in the System SI-PBA II.
- Assign IBIS models to the functional blocks (Controller and Memory) of these SPBSs and PAPBSs.
- Generate W-element transmission line model to represent pre-routed DDR3/DDR4 parallel bus interface.
- Connect blocks of SPBSs and PAPBSs, using the model connection protocol (MCP).
- Set analysis options, including channel simulation options before simulating these parallel bus systems.
- Set voltage and current probe points in SPBSs and PAPBSs.
- Set various types of sweeping parameters.
- Run simulations and sweep simulations.
- Generate simulation based reports with tables and waveforms.
- View tables, 2D plots, eye diagrams, BER Eye plots, Bathtub plot, impulse and ramp responses of the DDR4 channel, etc.
- Analyze simulation based results, waveforms and tables to evaluate the power and signal integrity performance of the SPBSs and PAPBSs.
- Modify the PAPBS model by replacing the S-Parameters model of the parallel bus interface by its broadband circuit model/S-Parameters model of reduced band width, by adding another memory block(s), by replacing IBIS models of the controller and memory blocks, etc.
- Run simulation of the modified SPBSs and PAPBSs and generate simulation based results.
- Compare power and signal integrity performance of the modified SPBSs and PAPBSs, based on the waveforms, timing parameters in the tables of the generated reports.
Software Used in This Course
SystemSI Parallel Bus Analysis II (SystemSI - PBA II)
Modules in this Course
Simple Parallel Bus System
Electrical engineers and PCB designers involved with design- oriented modeling, simulation and analysis of pre-routed and post-routed high-speed DDR3/DDR4 parallel bus systems
You must have:
- A practical understanding of power and signal integrity issues of high-speed DDR3/DDR4 parallel bus systems, and
- Basic understanding of transmission lines and S-parameters