MIPI® SPMIsm Verification IP for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® SPMIsm (System Power Management Interface) protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for SPMI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SPMI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for SPMI v1.0 and v2.0.

MIPI SPMI diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name



  • Multiple subordinates and multiple mains topology


  • High Speed and Low Speed device classes

Main Connection

  • Main Connection by Detection of SSC, Bus Idle, Bus arbitration

Main Arbitration

  • Main Priority and Secondary arbitration requests

Subordinate Types

  • RCS and NRCS subordinates

Sl Arbitration

  • Supports A-bit and SR-bit subordinate arbitration requests

Packet Generation

  • Command, Address, Data, No Response Frame, SPMI commands

Device Address Types

  • Supports MID, GSID, USID device addresses


  • ACK/NACK mechanism as per version 2.0 specification

Arbitration Generation

  • Capability to generate simultaneous Arbitration request scenario

Error Injection

  • Injection/detection of errors for example parity errors/ noise spike at different arbitration level


  • Generation and detection of SSC (Sequence Start Condition)

Event Notification

  • Arbitration win/lost, error detection, command/data/address frame sent, subordinate A/SR bit eligibility status

Simulation Test Suite

Comprehensive testsuite with coverage model for simple and fast design and verification bring-up.

Master your tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with Online trainings, VIP Portal, application notes, and troubleshooting articles