Best in class MIPI® DSI-2sm Verification IP for your IP, SoC, and system-level design testing.

In production since 2008 on dozens of production designs.

Cadence provides a mature and comprehensive Verification IP (VIP) for the DSI-2sm protocol, which is part of the MIPI® family. Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP for DSI-2sm Protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for DSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI for DSI v1.3.1,  DSI2 v1.0, v1.1, DSI2 v2.0 and DPHY v1.2, v2.0, v2.1 and CPHY v1.1, and v1.

MIPI DSI-2 diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection at DSI, D-PHY, and C-PHY levels
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name Description

Receiver and Transmitter Verification

  • Verifies both DSI processor and peripheral

Physical Layer

  • Includes the MIPI D-PHYsm/C-PHYsm VIP for physical layer verification

PHY Interfaces

  • Serial and Parallel PHY interfaces

Data Lanes

  • 1 to 4 data lanes

Power State

  • High-Speed and Low Power data transmission

LP Capabilities

  • Ultra-Low Power mode (ULPM), triggers and LP data transmission

Transmission of Multiple Packets

  • Several merged packets in a single PHY transmission

Traffic Modes

  • Sending and receiving of DSI packets and frames in command mode and all video modes

Accurate Video Mode Timing

  • Generation and checks of accurate video mode timings

Control of Payload Data

  • User can control the frame and packet payload


  • Enables data scrambling in order to mitigate the effects of EMI and RF self-interference

Built-In Test

  • Supports PRBS test debug pattern for C-PHY

Control Packet Data During BLLP Period

  • Enables the user to control the packets that are sent during BLLP periods in non-VACT lines

VESA Display Stream Compression Support

  • Performs actual compression/decompression and provides a set of checkers for monitoring of DSC-related traffic

Variable PPI HS Data Bus Width

  • Supports 8-, 16-, and 32-bit PPI HS data bus widths over D-PHY 2.0
  • Supports 16 and 32 PPI HS data bus widths over C-PHY

DSI2 v 1.1

  • Supports D-PHY specification 2.1 and C-PHY specification 1.2

DSI2 Over D-PHY 2.1

  • HS-Idle State, Alternate Calibration, and Preamble sequence

DSI2 Over C-PHY 1.2

  • ALP transactions and calibration sequence

Video Frame for BTA and ULP during BLLP

  • Supports sending and receiving BTA/ULP within video frame blanking period

DSI2 v2.0 Data Types

  • Data types SEP and PENP from Processor to Peripheral and vice versa and video frame data type PKT_PIXEL_STREAM_20_YCBCR422

Video Command Mode Seamless Transactions

  • Enables VIP to change command to video and video to command mode based on DCS command

Simulation Test Suite

Extensive testsuite, coverage model and verification plan with clear linkage to the specification for simple and fast compliance testing.

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