Best-in-class Arm® SWD Verification IP (VIP) for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug Interface Specification. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms incorporating the latest protocol updates with integrated automatic protocol checks and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for SWD runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specification: SWD v1 and v2 as per Arm Debug Interface specification v6.0 (ADIv6.0).

AMBA SWD diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Generates constrained-random bus traffi with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Packet tracker creation for easy debugging

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name


Serial Wire Debug Port

  • Fully supports SWD-DP functionality as per section B4 of ADIv6.0 specification

Serial Wire/JTAG Debug Port

  • Fully supports SWD-related functionality of SWJ-DP as per section B5 of ADIv6.0 specification, including customizable JTAG/SWD switching mechanism

Error Injection

  • Ability to inject errors at the single-bit level (Parity, Start bit, Park bit, and so on)

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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