Best-in-class Arm® AMBA® ACE Verification IP (VIP) for your IP, SoC, and system-level design testing

Cadence provides a mature and comprehensive Verification IP (VIP) for the ACE specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for ACE provides a framework for system-level coherency, integrated automatic protocol checks, and coverage model. Cadence provides an integrated solution for interconnect verification that supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP provides a mature, highly capable compliance verification solution making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for AMBA ACE is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA ACE-Lite, AMBA 5 ACE, AMBA 5 ACE-Lite, AMBA 5 ACE-LiteDVM interfacesת AMBA ACE issues F, G, and H.

AMBA ACE diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Provides comprehensive checking and coverage model
  • Includes embedded memory model in Subordinate models
  • Includes embedded cache model in Manager models
  • Packet tracker for ease of debugging
  • Seamless integration with System Verification Scoreboard (SVD) and System Performance Analyzer (SPA)

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name



  • Support for ACE-Lite configuration; automatically modify the agent accordingly

Data and Address Widths

  • Supports all legal data and address widths

Multiple Agents

  • Supports any number of agents

Automatic Subordinate Responses

  • Support for automatic Subordinate responses

Barrier Transactions

  • Supports monitoring and driving of barrier transactions

Cache Model

  • Cache model in both active and passive manager agents including cache state checks

Transmission Order Control

  • Support for control over the order of transmission of read transfers and write responses

Data Before Address

  • Supports sending of data before address transactions

Delay Control

  • Sets the delay between the items on the channels

DVM Transactions

  • Supports monitoring and driving of DVM (Distributed Virtual Memory) transactions

Exclusive Access

  • Supports monitoring and driving of all exclusive transactions

Manager Signals Control

  • Support for control over the values of the burst, transfer, snoop, and snoop response signals

Subordinate Response Control

  • Support for control over the values of the signals in the read data channel

Snoop Filter

  • Supports connection to a snoop filter

Transaction Types

  • Supports monitoring and driving of all read and write transactions

Atomic Transactions

  • Supports atomic transactions

Cache Stashing

  • Support for cache stashing

Other Signaling

  • Support for Wake-up Signaling, User Loopback Signaling, QoS Accept Signaling, and Coherency Connection Signaling


  • Supports Distributed Virtual Memory Extensions for Armv8.1 architecture

Untranslated Transactions

  • Support for Untranslated Transactions

Non-Secure Access Identifiers

  • Support for Non-Secure Access Identifiers


  • Supports Memory Partitioning and Monitoring functionality


  • Supports Memory Tagging Extensions functionality

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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