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Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Functional verification entails changing the state of a logic design and measuring that the response generated by the design is correct. Verification environments change the state of designs by driving stimulus in the form of directed or constrained random inputs. But when are you done? In verification, signoff is the process of defining criteria, and objectively measuring metrics against the criteria as the development progresses, until they match.
Metric-Driven Signoff is a unique Cadence® methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development. While milestones and metrics vary by design type and end application, the final verification signoff will at, a minimum, contain the criteria and metrics within a flexible, human-readable, user-defined organizational structure. Automated data collection, project tracking, dashboards, and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.
Common pre-silicon IC stages will often consist of the following milestones leading to signoff.
Designer Handoff Milestone
The designer’s checklist will incorporate basic functional and structural checks. The most fundamental of these checks are sanity tests, FSM tests, and lint checking, often adding dynamic assertions to verify key design properties. Tools used at this stage normally include:
IP Verification Milestone
From designer handoff, verification engineers will utilize the industry-standard Metric-Driven Verification (MDV) methodology for automating measurement compared to the goals. Criteria are captured in an executable verification plan, and metrics are collected after tests are run, then back-annotated to this plan. For IP designs, metrics will typically be around coverage (functional and code), regression tests, bug rate, and corner cases, and often augmented with formal techniques from the JasperGold platform. The vPlan within the vManager™ Metric-Driven Signoff Platform is used to organize data and automate the data collection. Tools used at this stage may include:
SoC Verification Milestone – Verification teams will utilize the proven multi-engine Metric-Driven Verification methodology for combining data from many different tools and technologies. The SoC signoff metrics include all IP-level metrics, adding toggle coverage, fault coverage, connectivity, register, integration tests, analog or mixed-signal tests, full-chip use cases, power, performance, and chip benchmarks. The vPlan within the vManager platform is used to organize data and automate the data collection. Tools used at this stage may include:
Metric Driven Signoff
Metric-driven signoff is defined as the final stage of all design and functional tests prior to physical implementation or coinciding with tapeout. The signoff stage includes all milestones and metrics from previous stages, plus adds all final structural checks such as clocking and low power. This final signoff stage will add gate-level tests, state machine (FSM), clock (CDC), synthesis, X-prop, failure mode (fault) testing, pre-silicon power measurements, and more as required. The vPlan (figure 1) and vManager platform can be used to collect and organize this data and enable a comprehensive Metric-Driven Signoff environment, with automatic data collection, manual checklists, and manual test result entry. Tools used at this stage may include:
Related Products
System Design and Verification Tools
