- Combines traditional RTL structural lint and formal analysis, deriving rich property-based functional checks from the RTL automatically
- Helps eliminate common functional design errors ahead of full unit-level or chip-level verification
- Fully integrated with the powerful Visualize debug environment, utilizing proven formal intelligence to reduce violation noise, speed debug, and improve waiver handling
Register-transfer level (RTL) designers often need to perform basic verification as soon as enough RTL is available, rather than waiting for testbench availability and before handing off the design to verification specialists. Assertion-based verification (ABV) can support an expedited workflow, but writing assertions demands specialized knowledge and can be very time-consuming even for experts.
Saving many weeks of tedious, error-prone work, the Cadence® Jasper™ Superlint App automatically generates high-value functional checks based on your RTL—no testbench or stimuli are required. This augments the wide range of structural lint and DFT checks that are also available with the Jasper Superlint App. Doing this wide range of checks early during RTL development helps designers to do a much more comprehensive RTL signoff leading to significantly improved RTL quality. The Jasper Superlint App is designed to be low noise and provides a lot of productivity features for designers to efficiently manage the violations.
Checks available in the Jasper Superlint App include:
- Comprehensive set of structural lint checks, e.g., naming, coding style, simulation-synthesis mismatch, synthesis
- Comprehensive set of DFT checks (both shift and capture mode) to ensure design is testable
- Best-in-class auto-formal checks, e.g., dead-code, FSM reachability/deadlock/livelock, bus contention, case, arithmetic overflow, and out-of-bounds index
Bottom line: The Jasper Superlint App helps eliminate common functional design errors and makes sure the code is clean before verification starts, improving design quality, and shortening the overall schedule.
- Interactive or batch modes are fully supported
- Violations are grouped to enable efficient analysis
- Uses unique JasperGold Visualize™ Interactive Debug Environment to let you focus on disposition of violations and provides easy specification of waivers
- Violation information and waivers are persistent for noise reduction during follow-on runs
- Context-sensitive debug capabilities are provided based on the type of violation, e.g., schematic for structural/DFT violations, FSM graph for FSM-related violations and waveform for auto-formal violations
- Unique capability to leverage formal to refine lint results helps reduce noise and makes the violation analysis much more productive
"With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”
Hobson Bullman Vice President and General Manager, Technology Services Group, ARM