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Key Benefits
- Enterprise-level reliability and scalability, with 5X greater emulation throughput
- Better resource utilization via advanced virtual target relocation and job re-shaping capabilities
- 92% smaller footprint via rack-based blade architecture
- Secure, scalable, and on-demand access with Palladium Cloud
Verification has become the biggest challenge in SoC development. However, traditional verification tools haven’t kept pace with how quickly SoC and ASIC design size and complexity are growing. Simulators slow to a grind as RTL and gate design size increase. This, in turn, delays system integration and extends the overall verification cycle.
As the industry's first datacenter-class emulation system, the Palladium® Z1 platform bridges the verification productivity gap to accelerate verification of SoCs, subsystems, and IP blocks, as well as system-level validation.
Compared to the previous generation, the platform, which brings together simulation acceleration and emulation technologies, delivers up to 5X better emulation throughput and, on average, 2.5X better workload efficiency than the closest competitor.
Palladium Z1
Easy to manage and scale, the platform:
- Compiles databases for different workloads, with up to 140MG per hour compile times on a single workstation
- Allocates as many workloads as possible
- Runs workloads based on priorities
- Debugs for both pre- and post-silicon bugs
Smart Emulation Resource Utilization
The way that the Palladium Z1 platform manages emulation resources can save you time and effort. The platform’s unique virtual target relocation capability, along with advanced job shaping allocation, avoids recompiles by allowing payloads to be allocated into available resources at runtime. The platform can execute up to 2304 parallel jobs with 4 million gate granularity and scales to 9.2 billion gates.
Compared to the Palladium XP II environment, the new platform offers an up to 44% reduction in power density, along with a reduction in power consumption per emulation cycle by a factor of three or more. The power advantages are a result of:
- An average of 2.5X better system utilization and number of parallel users
- Up to 5X better emulation throughput
- Up to 140MG per hour compile times
- Superior debug depth and upload speeds
Its rack-based blade architecture results in a 92% smaller footprint and 8X better gate density, compared to the Palladium XP II platform. The Palladium Z1 processor-based compute engine is also designed with massive parallelism, delivering 4X better user granularity than its nearest competitor.
Through a compile flow, the Palladium Z1 platform is congruent with the Protium S1 FPGA-Based Prototyping Platform and the Protium X1 Enterprise Prototyping Platform for software development, system validation, and hardware regressions.
Features
- Processor-based compute engine and Verification Xccelerator Emulator (VXE) software deliver up to 2X faster compiles, run higher performance verification, and support flexible new use models
- Virtual Verification Machine (VVM) supports interactive offline debug
- Cadence Xcelium® simulator users can hot-swap from simulation to acceleration without recompilation
- Enables quick bring-up via fast, automated, intelligent compiler
- Facilitates quick system-level bring-up with comprehensive Cadence SpeedBridge® Adapter portfolio and Accelerated Verification IP
- Enables dynamic power analysis and verification via interoperability with the Cadence Joules™ RTL Power Solution
- Supports pre-qualified and configured Emulation Development Kit (EDK) portfolio for USB and PCI Express® for rapid driver development and design verification
- Supports coverage and metric-driven verification
- Features hybrid environment for early hardware/software validation of design and embedded testbenches for comprehensive verification and re-use methodology
- Provides high-level synthesis with Cadence Stratus™ High-Level Synthesis (HLS), so you can integrate high-level abstraction models into the system verification environment
- Supports case-based verification with Cadence Perspec™ System Verifier for SoCs that reduces complex system-level coverage-driven test development time
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Related Products
- Cadence Verification Suite
- Palladium Hybrid
- Palladium Dynamic Power Analysis
- Protium S1 Desktop Prototyping Platform
- [REDIRECT] Protium X1 Enterprise Prototyping Platform
- SpeedBridge Adapters
- Xcelium Logic Simulator
- VirtualBridge Adapters
- Emulation Development Kit
- Accelerated Verification IP
- QuickCycles Service
- Palladium Cloud
- Virtual Debug Interface for Software Debuggers
Resource Library
Video (35)
- Dynamic Duo (short version) in 16x9
- AMD Designs 3rd-Gen EPYC Server Processors for HPC with Dynamic Duo
- Pushbutton migration from emulation to prototyping based on Protium platform
- Conquer IP Functional Verification with Formal and Simulation Approach
- +Perspec on Palladium - New Efficient Bus-Performance Verification Techniques
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- Do’s and Don’ts of Emulating Next-Generation Multi-Billion-Gate Ethernet and InfiniBand Interconnect Devices While Optimizing Verification Productivity and Meeting Development Schedu
- GSP Emulation with Palladium Platform and Prototyping with Protium Platform
- SoC Firmware Debugging Tracer in Emulation Platform
- Improving Firmware Validation Productivity and Debug Efficiency Using Palladium Z1 Platform and Indago Debug Analyzer
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- Create Palladium Design Equivalent to Both Specification and Gate Implementation on Silicon
- 400G以太在Palladium加速器上的仿真加速实践
- DFT DFD verification acceleration on Palladium
- Accelerate Baidu Kunlun AI chip development based on Palladium Z1 platform
- Accelerating software bring up and debug on emulator with a fluent migration from Palladium to Protium
- Fujitsu Designing the World’s Leading Innovations with Cadence Intelligent System Design
- Mom, I Have a Digital Twin? Now You Tell Me?
- Marvell Gains High Confidence for Silicon Tapeout Using Palladium Emulator to Validate Processor
- Early Firmware Development on Palladium and Protium, Enables 1st Silicon Success at Toshiba Memory
- Green Hills Software Partners with Cadence to Accelerate Embedded System Safety and Security
- Building better aerospace and defense electronics: emulate before you fabricate
- Cadence Delivers Verification Throughput
- Palladium and Protium Dynamic Duo
- Accelerate Your Time to Debug Root Cause
- NVIDIA Partners with Cadence to Overcome Chip Design Challenges
- The Palladium Solution and SoC Emulation for 16nm Automotive Devices at NXP
- Using the Cadence VirtualBridge Emulator with the Palladium Platform
- Taking FPGA-Based Prototyping to the Next Level
- CDNLive India – A Closer Look at State-of-the-Art Verification Techniques and Methodologies
- Palladium Z1: Advanced Job Re-shaping
- Emulating Nvidia GPUs
- NVIDIA Handles Complexity with Palladium Z1 Platform
- Verify Smarter with Industry's First Datacenter-Class Emulation System
- National and Cadence Building a More Efficient Chip Design Flow
Datasheet (11)
- Memory Model Portfolio for Palladium Series Datasheet
- VirtualBridge Adapter for PCI Express 2.0/3.0 Datasheet
- Virtual JTAG Virtual JTAG Debug Interface Datasheet
- Palladium Z1 Enterprise Emulation Platform Datasheet
- Cadence SpeedBridge Adapter for USB 2.0 Host Datasheet
- Cadence SpeedBridge Adapter for PCI Express 3.0 Datasheet
- Cadence SpeedBridge Adapter for Serial ATA (SATA) Datasheet
- SpeedBridge Adapter for USB 3.0 Devices Datasheet
- Cadence SpeedBridge Adapter for Ethernet Datasheet
- Cadence SpeedBridge Adapter for Serial-Attached SCSI (SAS) Datasheet
Press Releases (20)
- Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform
- Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development
- Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
- Cadence Accelerates Arm-Based Server Development by Automating Arm Pre-Silicon Bare Metal Compliance Testing
- Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform
- Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development
- Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform
- Cadence Announces Next-Generation JasperGold Formal Verification Platform
- Media Alert: Cadence to Showcase System Design and Verification Solutions at DVCon US 2015
- M31 Technology Adopts Cadence Verification IP to Achieve 2.5X Faster Verification
- DMP Adopts Cadence Palladium XP Platform to Accelerate High Performance Graphic IP Core Development
- Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
- Cadence Introduces Automotive Functional Safety Verification Solution, Reducing ISO 26262 Compliance Preparation Effort by up to 50 Percent
- CSR Selects Cadence Palladium XP Platform for Development of ARM-based Automotive Infotainment Systems
- HiSilicon Expands Cadence Palladium XP Platform Usage For Mobile and Digital Media SoC and ASIC Development
- Cadence Redefines Verification Planning and Management with Incisive vManager Solution
- Ricoh Selects Cadence Palladium XP Platform for Next-Generation Multifunction Printer SoC Development
Customer Presentation (8)
- Pushbutton migration from emulation to prototyping based on Protium platform
- Conquer IP Functional Verification with Formal and Simulation Approach
- +Perspec on Palladium - New Efficient Bus-Performance Verification Techniques
- Productive Design: Hardware/Software Co-Verification with Virtual Debugging from Simulation to Prototyping
- SoC Firmware Debugging Tracer in Emulation Platform
- Digital Twin Case Study: Applying Emulation-Based Verification of SoC Using Tactical Software
- 400G以太在Palladium加速器上的仿真加速实践
- Accelerate Baidu Kunlun AI chip development based on Palladium Z1 platform
Customers
Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.
Narenda Konda, Director of Engineering, NVIDIA
The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four-million-gate verification payloads to multi-billion gate designs.
Daniel Diao, Deputy General Manager of the Turing Processor Business Unit, Huawei
Training
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