Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating IP development, early software development, SoC integration, concurrent hardware/software development, and integrated system validation.
Productivity and Throughput
Improves verification productivity and throughput and increases team collaboration, allowing users to find and fix the most bugs per dollar invested
Provides smart verification management through automation, debug, tracking, management, and measurement of verification tasks across verification engines
Supports a broad range of industry standards, third-party tools, and integration with our ecosystem partners, including Arm and Green Hills
The Verification Suite is comprised of core engines and verification fabric technologies that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.
Formal and Static Verification
An exhaustive form of verification that requires no testbench, saves months of verification effort, and finds more bugs at an earlier stage of the design
Simulation and Testbench
Leveraging single and multi-core simulation performance and our testbench verification tools to enhance performance, productivity, and quality
Comprehensive system-level verification that provides high degree of control and visibility, applies system-level stimulus to the design, and verifies the behavior of the system
Rapidly bring up a prototype and provide a pre-silicon platform for early software development, system validation, and throughput regressions
Planning and Management
Achieve a predictable path to verification closure with automated planning and metrics management, and comprehensive coverage at block, chip, and system levels
Shorten simulation run time with VIP and memory models optimized for the IP, SoC, and system-level testing required for today’s designs
Sophisticated solutions to address RTL, testbench, VIP, and SoC verification debug needs
Solutions in the Verification Suite are pre-defined flows and best practices to address common challenges, including total throughput for the shortest project schedule, metric-driven signoff for quality, and application-specific challenges for mobile, networking and servers, automotive, consumer and internet of things (IoT), aerospace and defense, and other vertical segments.
Metric-Driven Verification Signoff
Helps you measure and sign off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development
Integrates analog behavior modeling and analog and digital solvers into one verification flow, allowing you to balance the right amount of accuracy and speed based on your design requirements
Verification for Arm-Based Designs
Helps you verify that your Arm®-based SoCs meet design intent using our the Cadence Verification Suite
Brings together all of the blocks as well as the power management features in your design so that you can verify your design, using the Cadence Verification Suite, with power intent