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Digital Design and Signoff

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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • 솔루션
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
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      • TRAINING
        • Custom IC / Analog / RF Design
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        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
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      • TRAINING
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Rigid-Flex

Minimize iterations for Rigid-Flex designs

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Rigid-Flex PCBs comprised of rigid and flexible substrates laminated together are inside a variety of small electronic products. Flexible PCBs (flex/Rigid-Flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. The Cadence® Allegro® and OrCAD® 17.2-2016 release enables several new capabilities that minimize design iterations and lower overall cost for flex and Rigid-Flex designs commonly used in automotive, consumer electronics, computing, communications, mobile, and wearable applications.

Key flex and Rigid-Flex features in the release include:
Stack-Up by Zone for Flex and Rigid-Flex Designs

Multiple zones can be created using the new Cross-Section Editor to represent Rigid-Flex/rigid PCBs. A physical zone is used to map an area of the design to one of the stack-ups created in the Cross-Section Editor. Zones automatically include associated keepouts and optional constraint regions and rooms. In-design rules coupled with this enhanced definition ensure that the design is correct by construction. An accurate definition of Rigid-Flex/rigid design can also be passed on to MCAD systems using IDX data exchange, eliminating unnecessary MCAD-ECAD iterations.

In-Design Inter-Layer Checks for Rigid-Flex Design

The number of conductive and non-conductive layers on flex and Rigid-Flex designs are increasing as the fabrication industry innovates to meet customer needs. This explosion of different types of materials and associated rules that are imposed on designers is increasing the amount of work PCB designers have to do to leverage the advances in Rigid-Flex technology.

New in-design inter-layer checks in the Allegro PCB Editor provide the ability to check geometries between two different layers. In typical PCB designs, various masks and surface finishes require verification of proper clearances and coverage. Rigid-Flex designs not only have the same mask and surface finish requirements, but also the addition of bend areas, stiffeners, and so on, which require special clearances or overlaps of materials, spacing, and design features. These objects that are represented on different subclasses require verification between these layers, and this capability is now supported using the inter-layer checks capabilities.

The inter-layer checks capability is a new design rule check (DRC) engine designed to check mask layer to mask layer geometry, as well as mask layer to surface metal. It allows checks for:

  • Coverlay to pad
  • Mask to pad
  • Precious metal to coverlay
  • Bend area/line to stiffener, component, pin, and via

 

 

The release introduces 12 new layers and 19 new surface finishes and allows users to enable checks against these layers using user-defined clearances or user-specified overlaps. Once enabled, the checks provide feedback during the layout process to avoid design-verify-redesign iterations. 

Enhanced Contour, Arc-Aware Routing

Enhanced Contour is a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. This feature has been improved over the legacy contour feature by removing a continuous dialog popup, introducing a simple canvas-based two-state click use model and enabling shove of existing connect lines. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners.

Related Links

  • Why Move Up to Allegro 17.2-2016? So How Does Your Design “Stack-Up”?
  • Why Move Up to Allegro 17.2-2016? Advanced Flex and Rigid-Flex Design Support 

Contact Us

Learn how a stack-up-by-zone feature provides faster, easier definition of stack-ups and improved MCAD-ECAD co-design while in-design inter-layer checking technology minimizes design-check-redesign iterations for flex and Rigid-Flex design

Avoid Costly Fabrication Errors with Real-Time Inter-Layer Checks Webinar

  • Related Products

    • Allegro PCB Designer
Resource Library

Press Releases (3)

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • New Cadence Allegro Platform Accelerates Design of Compact, High-Performance Products Using Flex and Rigid-Flex Technologies
  • Cadence Strengthens Allegro Technology Portfolio to Make Design Cycles Shorter and More Predictable

Datasheet (1)

  • Allegro PCB Design Solution Datasheet

Webinar (2)

  • Conquer High-Speed Interfaces Faster
  • Gain an Unfair Advantage - Make Better Products Faster with Cadence PCB Tools

White Paper (1)

  • Automating Inter-Layer In-Design Checks in Rigid-Flex PCBs White Paper
VIEW ALL
Videos

CadenceLIVE Taiwan: Rigid-Flex PCB Design and EM Analysis Using a Front-to-Back Cadence Flow

Rigid-Flex PCB Design and EM Analysis Using a Front-to-Back Cadence Flow

Enhanced Cadence AWR AXIEM EM Capabilities for IC and PCB: IC Inductor and 5G PCB Examples

CadenceLIVE Taiwan: RF to mmWave Front-End Component Design for 5G NR

Allegro PCB Symphony Team Design 17.2 Release

Team Source Your PCB Layout - Hassle Free Real-Time Team Design

News ReleasesVIEW ALL
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence DesignTrue DFM Ecosystem Connects Manufacturers with Customers to Ensure PCB Design Manufacturability Early in the Design Process 09/04/2018

  • Cadence DesignTrue DFM Ecosystem Connects Manufacturers with Customers to Ensure PCB Design Manufacturability Early in the Design Process 09/04/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • New Cadence Allegro PCB DesignTrue DFM Technology Accelerates New Product Development and Introduction Process 09/12/2017

Blogs VIEW ALL
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