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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Verification

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Multiphysics System Analysis

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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PDN Design

Constraint-driven design with an integrated layout and analysis solution

Read Team PI Analysis White Paper
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Key Benefits

  • Team-based constraint-driven design flow: PCB layout specialists perform first-order PI analysis so the PI expert can focus on advanced analysis tasks
  • Automate the AC and DC PI analysis set-up, and reuse previous set-ups to allow design changes to be quickly and easily analyzed
  • Easily identify layout and routing changes necessary to meet PDN-specific requirements with DRC markers and cross-probing

In PCB design, DC analysis is vital as numerous factors combine to exacerbate the problem of power integrity. Core voltage levels continue to drop; 1.2V and less are now common. As voltage is reduced, current requirements typically increase (IR drop = I * R). The miniaturization of electronics results in fewer layers and higher densities, thus reducing the available area for power nets. And antipads around vias perforate the planes and can overlap, creating the “Swiss cheese” effect.

In addition, there are the power delivery network (PDN) challenges for a PCB designer, starting with the multiple instructions from hardware designer or power integrity (PI) engineer that are communicated by email, phone call, rules of thumb, etc. The designer must apply all of those instructions and rules to multiple power supplies. Having done that, the designer must then attempt to fulfill additional requests, such as “Can you shrink it by 20%?”, “Can you remove two plane layers and five capacitors?”, and that age-old favorite, “Can you do it yesterday?”

Complex boards can have dozens of power rails, hundreds of power nets (including filter nets) and even more components that make up the PDN. Sorting through hundreds of pages of schematics to ensure that the PDN is logically connected is one pain point. However, it may become even more painful on the back-end of the design process when power integrity analysis requires that all those nets and components be specified and modeled for power integrity analysis. This may take days or even weeks just to setup.

An additional challenge is how the design issues are communicated: How does the PI engineer communicate issues and guidance to the PCB designer? How does the PCB designer communicate solutions to the PI engineer? How can the PCB designer determine if a solution is good? Fortunately, integration features are available to assist the PCB designer and PI engineer with these design and communication issues. In addition, the PCB designer has tools available to him to automatically calculate first-order electrical constraints to help get started if the PI engineer has not yet communicated the guidance.

PowerTree Graphical Environment

The Cadence Allegro® PowerTree™ technology allows the PCB layout specialists and hardware designers to graphically view source/sink definitions, discrete values, model names, net names, decoupling capacitor values, target impedance constraints, and more in the logical PDN topology. 

pdn-design-fig06-600px


Hardware designers can perform early analysis sanity checks at the push of a button. By using schematic data, they can determine if the PDN topology has been properly captured to meet the design criteria. 

PowerTree Viewer


By empowering hardware designers and PCB layout specialists to perform simple analysis, PI experts can focus on more specialized analysis. With automated setup from PowerTree technology, PI experts and non-experts alike no longer need to spend days or weeks setting up PI analysis. Applying the PowerTree data to the physical design makes simulation as easy as the click of a button.

Integration Features

Decoupling capacitor placement rules require the PI expert to perform analysis to determine the ideal de-cap scheme for each IC. In addition, PI expert must creates PI constraint sets to guide the PCB designers decap placement.

Screenshots showing how the Power Feasibility Editor is used within the Allegro PCB Designer


DRC markers determined by PI designers’ rules are annotated to the Cadence Allegro PCB Designer. These markers enable the PCB designer to understand PDN issues discovered by the PI engineer and address them.

Screenshot showing DRC Marker annotations in Alllegro PCB Designer


Cross-probing between Allegro PCB Designer and analysis results enables the PCB designer to use the visual analysis results to determine what needs to be changed in the PCB, such as increasing the size of power shapes, adding vias, adding planes, etc.

Cross-probing between Allegro and analysis results enables the PCB designer to use the visual analysis results to determine what needs to be changed in the PCB


Re-using the PI expert's set-up enables the PCB designer to change and re-analyze the design, including the changes to the original set-up.

Re-using the setup done by PI expert enables the PCB designer to make changes and re-analyze to determine if the PI problem is resolved without another setup

Allegro/Sigrity Integration

Allegro Sigrity™ PI Base integrates Allegro and Sigrity technology for PI analysis of PCB, IC package, and system-in-package (SiP) designs, and enables constraint-driven design with an integrated layout and analysis solution. The Allegro Sigrity PI Base’s primary advantages include:

  • Proven Sigrity analysis engines
  • Automated set-up using PowerTree data captured from the schematic
  • Industry’s first constraint-driven PI design process to drive decap selection and placement
  • Automated cross-probing configuration after DC analysis to easily identify and resolve IR drop issues in physical layout
  • Targeted for layout designers and PI engineers
  • Add-on options for detailed analysis, compliance, and assessment
Allegro technology together with Sigrity power analysis technology
WEBINAR

How a Team-Based Approach to PCB PI Analysis Yields Better Results

VIEW WEBINAR

Seagate reduces IR drop, accelerates its review cycles, and lowers product cost with Allegro and Sigrity tools

  • Related Products

    • Sigrity XtractIM
    • Voltus IC Power Integrity Solution
    • Allegro PCB Designer
    • Celsius DC
    • Sigrity Aurora
Videos

Sigrity Tech Tip: How PCB Designers Can Find and Fix Power Integrity Problems

Sigrity Tech Tip: How PCB Designers Can Create Initial PDN Constraints Without Becoming a PI Expert

DesignCon 2017: Sigrity 2017 Portfolio Highlights

Multi-Board Electrical and Thermal Co-simulation using Sigrity PowerDC

Allegro Sigrity OptimizePI - Automated Decap Design

Sigrity Tech Tips: How to Share Power Delivery Network Design Analysis Across the PCB Design Team

News ReleasesVIEW ALL
  • Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers 11/13/2018

  • Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies 10/02/2018

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board 05/30/2017

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

Blogs VIEW ALL
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