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Allegro PCB Editor

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New Capabilities for Flex and Rigid-Flex Designs
  • Stack-up by zone for flex and rigid-flex designs 
    In the Allegro® PCB Editor 17.2-2016 release, multiple zones can be created using the new Cross-Section Editor to represent rigid-flex-rigid PCBs. A physical zone is used to map an area of the design to one of the stackups created in the Cross-Section Editor. Zones automatically include associated keep-outs and optional constraint regions and rooms. In-design rules coupled with this enhanced definition ensures that the design is correct by construction. An accurate definition of rigid-flex-rigid design can also be passed on to MCAD systems using IDX data exchange, eliminating unnecessary MCAD-ECAD iterations.

Image showing Cadence Allegro Rigid Flex capabilities in UI

  • In-design inter-layer checks for rigid-flex design
    Number of conductive and non-conductive layers on flex and rigid-flex designs are increasing as the fabrication industry is innovating to meet their customer’s needs. This explosion of different types of materials and associated rules that are imposed on designers are increasing the amount of work PCB designers have to do to leverage the advances in rigid-flex technology. The Allegro PCB Editor 17.2-2016 release introduces new in-design inter-layer checks that provide the ability to check geometries between two different layers. In typical PCB designs, various masks and surface finishes require verification of proper clearances and coverage. Rigid-flex designs not only have the same mask and surface finish requirements but the addition of bend areas, stiffeners, and so on, which require special clearances or overlaps of materials, spacing, and design features. These objects that are represented on different subclasses require verification between these layers, and this capability is now supported using the inter-layer checks capability. The inter-layer checks capability is a new DRC engine designed to check mask-layer-to-mask-layer geometry, as well as mask layer to surface metal. It allows checks for:
    • Coverlay to pad
    • Mask to pad
    • Precious metal to coverlay
    • Bend area/line to stiffener, component, pin, and via

    Image showing Cadence Allegro inter-layer checks for Rigid Flex capabilities

    The Allegro 17.2-2016 release introduces 12 new layers and 19 new surface finishes, and allows users to enable checks against these layers using user-defined clearances or user-specified overlaps. Once enabled, the checks provide feedback during the layout process to avoid design-verify-redesign iterations.

Image showing Cadence Allegro Rigid Flex Design Dialog in Allegro UI

  • Enhanced Contour and arc-aware routing 
    Enhanced Contour is a more efficient method to add routing during Add Connect by following an existing connect line or a route keep-in. This feature is an improvement over the legacy Contour feature by removing a continuous dialog popup, introducing a simple canvas-based two-state click use model and enabling Shove of existing connect lines. Transitions between the non-contoured and the contoured routing are smoothed for line or arc corners.

Screenshot of Cadence Allegro version control capabilities

Cross-Section Editor

In the Allegro PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned leveraging the underlying spreadsheet technology found in Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design.

The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay. The Cross-Section Editor provides total thicknesses for each stackup in terms of accumulated conductor layers, as well as an option with mask-layer thicknesses included.

Other enhancements of the Cross-Section Editor include a graphical image of the stackup construct that is available in a dockable window. The stackup image includes functionality to reverse drill direction. Grid editing enhancements include functions to add layer pairs or a user-defined number of layers.

Image showing Allegro cross-section editor UI

Dynamic Concurrent Team Design

For dense PCB designs that have many constraints on critical signals—designs with high-speed interfaces or designs that have a limited area to route signals on—many designers can spend up to 70% of the overall design cycle on routing, tuning, and optimization of signals. The new Allegro dynamic concurrent team design capability focuses on shortening the largest portion of the PCB layout design cycle. It provides interactive etch-editing capabilities as well as unique Allegro TimingVision™, auto-interactive delay, and phase-tuning capabilities that have been proven to shorten the time needed to route advanced high-speed interfaces such as DDRx and PCI Express® (PCIe®) by up to 80 percent. 

Image showing concurrent team design features in Allegro

The new Allegro PCB Team Design Option provides dynamic concurrent PCB team design for multiple PCB designers to work on the same design at the same time without any set-up requirements. The new dynamic concurrent-team-design capability provides two use models—the informal mode and the structured mode. In the informal mode, any user can start editing the design using the dynamic concurrent mode, and other users can join or leave the session in progress as needed. A structured mode is set up on a server and all users that want to concurrently work on the same design can do so by connecting to that session, with the ability to join or leave the session at any time.

New Padstack Editor

In the Allegro 17.2-2016 release, a new Padstack Editor has been introduced to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, backdrill padstacks, and also the commonly used padstacks.

  • The new Padstack Designer is a modern, easy-to-use interface to build padstacks. It includes tabs for specific padstack features.
  • New Padstack Usage Types include Bond Finger, Die Pad, Tooling Hole, Mounting Hole, Fiducial, etc.
  • New Pad Geometries have been introduced that include Rounded Rectangle, Chamfered Rectangle, Donut, and n-Sided Polygon
  • New Drill Features include a new “Square hole” ability to define actual drill size or tool identification to be used to drill the hole before plating. In addition, slot tolerances are divided into two sets, X tolerance and Y tolerance.

Image showing new Cadence Allegro Pad Stack Editor

Expanded In-Design Rules for Backdrill Vias

With the Allegro 17.2-2016 release, many improvements have been made to the backdrill process to assist the PCB designer in managing the backdrill vias/padstacks, route around the backdrill vias/padstacks with accurate DRCs, and real-time feedback. Backdrill data is now stored in the library padstacks and utilized at the design level during the analysis and backdrill-generation process. Padstacks that do not have pre-defined backdrill information can be automatically updated at the design level by entering the backdrill criteria prior to running backdrill. All backdrill data is available on the individual pin/via objects displayed on the canvas or by simply querying the object using Show Element, and generating the Backdrill Legends and detailed Backdrill Report. In addition, the setup time for backdrill can now be improved as a result of algorithms designed to create intelligent layer pairs.

Image showing how to define rules for backdrill vias in Cadence Allegro environment

Image showing how to edit expanded design rules for backdrill vias in Cadence Allegro

Tabbed Routing

Shrinking pin pitches are forcing narrower than usual trace widths. Coupled with an increasing number of pins on BGAs, single-ended and differential pair signals have to meander through the pin fields, often with arcs. Pin fields on large-pin-count devices are by nature full of voids on the reference plane, making it harder to control impedance on critical signals. The result is a higher impedance than desired on critical signals. Tabbed routing is a new routing strategy in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin-field/breakout region and crosstalk in the open-field region. This method enables longer trace lengths and use of smaller trace spacing. Tabbed routing is used for impedance control and to manage crosstalk in critical signals, enhancing signal quality and improving route channel utilization. The Allegro PCB Designer High-Speed Option enables tabbed Route Generation, Tab Count Validation, Tab Pitch Validation, Manage/Delete Tabs when traces are edited.

Image showing an example of designing tabbed routing in Cadence Allegro

Return Path Management Through Custom Via Structures

Allegro PCB High-Speed Option introduced six via structures for managing return path for critical differential signals during Add Connect in the Allegro 16.6-2015 release.

The Allegro 17.2-2016 release enhances the ability to add return path via structures during Add Connect by allowing users to use custom return path via structures. These via structures can be fine-tuned and verified using Sigrity technology, ensuring that right return path via structures are used in the design and shortening the time to verify that a design meets performance criteria for critical high-speed signals. 

The Create Via Structure feature allows you to create two types of via structures: standard and high speed. There is also an option available to automatically export an XML file, which can be used to import/export via structure definition in other PCB/SiP database and Sigrity technology.

  • Standard Via Structure: The Target Use Model is single net trace/via structure and fan-out.
  • High Speed Via Structure: The Target Use Model is differential pair via transitions with Return Path Vias and custom plane voids.

Image demonstrating how to view horizontal via structures in Cadence Allegro

Image showing an example of exml file structures as displayed in Cadence Allegro

Ease-of-Use Improvements in Allegro PCB Editor

In the Allegro 17.2-2016 release, several features have been enhanced to improve the ease of use of the Allegro PCB Editor. New enhancements include:

  • Visibility Pane with access to mask layers and zones: The Visibility Pane has been enhanced to allow designers access and control of layer content more quickly and more efficiently. Instead of a single stackup approach, the Visibility Pane now gives you quick access to easily configure and view different zone stackups.

Image showing how to choose color and visibility options in Cadence Allegro

  • Shape Edit Application Mode: The Shape Edit Application Mode is a tuned editing environment primarily designed to increase efficiency with shape boundary editing. This object-action environment simplifies the actions of sliding a shape edge, adding a notch or chamfering/rounding the corners.

Image showing how to set the shape edit mode in Cadence Allegro

  • Constraint Manager improvements:Many ease of use and productivity improvements have been made to the Allegro Constraint Manager, including:
    • Column Display Priority
    • Super Attribute ALL
    • Object Group Types
    • Hierarchical Layer Support
    • Alternate Rows Background Color
    • Constraints Grouping in Spacing and Same Net Spacing Domains
    • Show Group Members
    • Improved Constraint Difference Report UI
    • Drag and Drop Group Membership
Image showing improvements in the Cadence Allegro Constraint Manager interface

Contact Us

Explore rigid-flex features of Allegro PCB Editor where you can create multiple zones using the Cross-Section Editor to represent rigid-flex-rigid PCBs and stack-up by zone for faster, easier definition of stack ups and improved MCAD-ECAD co-design

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