Tensilica FloatingPoint DSPs with Low Energy Consumption and Excellent Performance Per Area

Cadence® Tensilica® FloatingPoint KP1/KP6 DSPs provide high-performance floating-point computation throughput with low energy consumption and small area footprint. The configurability and extensibility of Tensilica FloatingPoint KP1/KP6 DSPs give the SoC designers flexibility to configure a floating-point DSP that meets their performance requirements with low energy and small area budgets. Tensilica FloatingPoint KP1/KP6 DSPs are optimized for applications in battery-operated devices, AI/ML, AR/VR, motor control, smart sensors, sensor fusion, ADAS, autonomous driving, etc.

FloatingPoint KP1/KP6 DSPs
FloatingPoint KP1/KP6 DSPs

Key Benefits

Performance, Power, and Area

DSPs with exceptional PPA specifically designed for floating-point-centric processing

Ultra-Low Energy and Small

High performance with low energy consumption and small area


ISA consistent with super-high performance Tensilica FloatingPoint KQ7/KQ8 DSPs

Software Portability

Common floating-point ISA promotes easy software migration between DSPs

Extensible and Configurable

Customizable instruction set promotes differentiation and performance enhancement


  • VLIW parallelism issuing multiple concurrent operations per cycle
  • Xtensa LX Secure Mode
  • 128-bit and 512-bit SIMD
  • IEEE 754 vector floating-point
  • Performance optimized fused multiply-add (FMA)
  • 8b/16b/32b/64b integer ALU operations
  • Optimized for FFT operations
  • Enhanced complex data processing
  • Superior auto vectorization support
  • TIE for easy extension and further performance enhancement
  • Optimized Eigen, NatureDSP, Math, and SLAM libraries for easy software development


Cadence, through its Tensilica processor IP, brings together best-in-class products and services from industry leaders to help you accelerate the development of your SoC designs while meeting your demanding power and performance requirements. Browse the list of Tensilica processor IP service partners below.


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