Cadence® PHY IP for PCI Express® (PCIe®) 6.0 is a high-performance NRZ/PAM4 SerDes designed specifically for infrastructure and data center applications. The SerDes’s ultra-long-reach equalization and robust clock-data recovery capabilities allow it to achieve unparalleled performance and reliability. In addition, the SerDes IP features low data path latency and low power consumption, making it ideal for deployment in time-sensitive applications in high-performance computing (HPC), artificial intelligence and machine learning (AI/ML), data communications, networking, and storage systems.


Key Benefits

High Performance

DSP-based equalization and clock-data-recovery (CDR) offer unmatched channel loss handling performance and reliability


Highly configurable PHY with support for PCIe, CXL, and common electrical standards

Lowest Risk

Brings Cadence’s expertise in PAM4 and PCIe together in the implementation of this emerging standard

Ease of use

Fully verified, pre-integrated IP delivery, with package and signal integrity support and firmware for faster bring-up


  • Architecture optimized for HPC, AI/ML, storage, and networking
  • Ultra-long reach, low latency, and low power
  • Advanced DSP delivers unmatched performance and reliability
  • Comprehensive real-time diagnostic, monitor, and test features
  • Bifurcation support for x1, x2, x4, x8, and x16 lanes