64GTps PHY IP for PCIe 6.0 for TSMC 5nm FinFET
Designed specifically for infrastructure and data center applications
Power-Efficient
- Cadence PHY IP for PCIe and CXL is designed to provide the best-in-class power efficiency for the latest PCIe standards while meeting data and clock recovery requirements in high-speed, high-dB-loss, high-crosstalk channels
- Support for latest power-saving engineering change notices (ECNs).
Flexible
- The PHY IP is easily configurable to meet application needs for multi-link use cases.
- Support for Ethernet and PCIe protocols makes it versatile for most common applications in the high-performance computing space
- Controller IP configurable for application-specific needs
Designed for the Future
- PHY IP available in advanced FinFET process nodes
- Controller IP supports PCIe 6.0 and 5.0 and CXL with low latency
HPC/AI/ML
Increased data bandwidth per lane at improved power efficiency
Storage and Persistent Memory
Solutions for lowest active and standby power with lowest exit latency
Enterprise, Cloud, and Data Center Solutions
Scalable multi-protocol solutions with lowest active power, security, and remote access service (RAS) features
