The Cadence® Denali® HBM2E/2 PHY and Controller IP is silicon-proven and includes architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the data bandwidth. It is engineered to quickly and easily integrate into SoCs and is verified as part of a complete memory subsystem solution. The HBM2E/2 PHY and Controller IP is an ideal solution for artificial intelligence (AI), high-performance computing (HPC), and image processing applications.
Silicon characterization reports available
For data-intensive applications
Increased data integrity from error correction and optimized throughput of unique pseudo-channel interleaving
Low Power and Area
Low-power control and advanced low-power modes with power down and self-refresh