Multi-protocol Solution
DDR and LPDDR supported in a single IP
Highly Configurable
Application-specific parameters and floorplan optimization
Low Power and Area
Industry-leading PPA based on advanced architecture and implementation
Low Latency
For data-intensive applications
Reliable
Maximum system margin with advanced clocking and I/O architectures
Future proof
Cutting edge technology with the latest GDDR protocols and the highest data rates
News ReleasesVIEW ALL
Blogs VIEW
ALL
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How We Developed and Tested a Prototype DDR5 Interface
5/1/2018 Marc Greenberg -
LPDDR5 Next Gen High-Performance Low Power Memory Interface
4/2/2019 Kostadin Gitchev -
Get Introduced to the DFI 5.0 Specification
5/2/2018 MeeraC -
GDDR6 and HBM2E on Samsung Foundry – the SAFE Choice
10/28/2020 Paul McLellan -
HBI, a New Standard to Connect Your Chiplets
12/11/2020 Paul McLellan