DDR/LPDDR PHY and Controller

Cadence^® Denali^® DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput while balancing power consumption and minimizing area. The DDR/LPDDR PHY and Controller IP are developed and validated to reduce risk for the customer so that their SoC will work right the first time. Available as a product-optimized solution for specific applications such as DDR5/LPDDR5, DDR4/LPDDR4, DDR3/LPDDR3, and additional multiple protocol combinations.