Key Benefits
- Enables SSN bus simulations by creating power-aware IBIS models
- Enables million-bit channel simulations for SerDes with equalization using IBIS-AMI model creation
- Retains transistor-level accuracy in behavioral models
- Creates algorithmic models for equalizers without writing a single line of code
- Generates models compliant with the IBIS 7.0 specification
To keep up with the rapid advances in high-speed interfaces, design teams need to be able to run accurate, full-bus simulations that include running million-bit channel simulations to predict bit-error rate (BER) from a topology with dozens of bus signals connected through their common power delivery network (PDN). This means creating both power-aware IBIS models as well as IBIS-AMI models.
The Cadence Sigrity™ Advanced IBIS Modeling solution gives you the ability to create algorithmic models that describe the behavior of the equalizers in transmitters (TXs) and receivers (RXs), as well as the ability to convert a SPICE transistor model to a behavioral analog front-end of an IBIS model.
When combined with the Sigrity Advanced SI solution, users can simulate both serial links and parallel bus topologies with models created for the I/O devices that are accurate, efficient, and distributable to customers of semiconductor companies (i.e., systems companies).
The Advanced IBIS Modeling solution consists of three modules:
Sigrity Transistor-to-Behavioral Model Conversion (T2B)
The Sigrity T2B™ solution saves you time and preserves co-simulation flows that include broadband chip, package, and flow models, by giving you output models in IBIS 3.2, 4.2, 5.0, 6.0, and 7.0 formats, as well as in an accuracy-enhanced Sigrity behavioral model format. Also, the power-aware behavioral driver models generated by the Sigrity T2B solution further ensure accuracy and support highly efficient simulations using Sigrity Advanced SI technology, or other compatible solutions such as Cadence Spectre® and HSPICE simulators.
Sigrity AMI Builder
Sigrity AMI Builder technology has accurately modeled hundreds of SerDes and memory interface devices. The wizard-based approach walks the user through a series of questions and builds a block-based topology of equalization elements. The block-based modeling environment allows for monitoring the signal through each phase of the equalization.
The Sigrity AMI Builder technology has proven accuracy through lab correlation.
IBIS-AMI modeling engineers can focus on architecture instead of code and quickly turn around new versions of their AMI model. Integration with Sigrity SystemSI technology gives insight into how the device will behave in its target system.
Sigrity SystemSI Technology
The Sigrity SystemSI™ environment works in three modes. First, a general topology environment for creating signal testbenches. Second, a serial link mode where the focus is on differential pair topologies and confirming that signals behave within the compliance of multi-gigabit serial link interface specifications. And third, a parallel bus simulation environment where dozens of signals can be simulated switching simultaneously along with the PDN and voltage regulator module (VRM). This technology complements the IBIS modeling environment in that model developers can see how their customers will use the IBIS models to model their systems.
Features
- Verifies behavioral model accuracy versus the original transistor model with an included time domain simulation wizard
- Accuracy checks are included as part of the model conversion process
- Highly automated and easy to use for those familiar with available IBIS model formats
- All IBIS BIRD95/BIRD98 power-aware effects are included
- Wizard-based approach guides the user through the creation of an IBIS-AMI model
- IBIS-AMI models are automatically compiled and created for Windows and Linux implementations
