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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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System Analysis

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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • System Design and Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Formal and Static Verification
          • Emulation
          • Planning and Management
          • FPGA-Based Prototyping
          • Simulation
          • Software-Driven Verification
          • System-Level Verification IP
          • Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • System Analysis
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • 솔루션
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Sigrity Advanced PI

Accelerating PDN designs

  • Overview
  • Videos
  • News and Blogs

Key Benefits

  • Reduces cost and time by identifying potential problems early with both pre-route and post-route
  • Ensures reliable power delivery by verifying AC, DC, and power-ripple analysis
  • Optimizes a PDN across the board/package interface
  • Easily addresses system-level power analysis challenges with a block-based schematic editor

To help you quickly validate the sufficiency, efficiency, and stability of the power delivery network (PDN), Cadence® Sigrity™ Advanced PI allows power integrity (PI) experts to perform PDN verification from each power source to each sink across multiple boards and packages.

Cadence Allegro® PowerTree™ technology lets you set up the analysis before the physical design process and validate the bill of materials defined during the logical design stage. As the physical implementation proceeds, the set-up captured in the PowerTree environment can be reused, essentially making DC and AC power integrity analysis a push-button process at each design stage.

Figure 1: Accurately simulate problematic real-world structures such as cutouts, via fields, wire bonds, and neck downs

Thermal-Aware DC Analysis

Sigrity PowerDC™ technology provides an efficient DC analysis for signoff of IC package and PCB designs, including electrical/thermal co-simulation to maximize accuracy. Sigrity PowerDC technology quickly pinpoints excessive IR drop along with areas of excess current density and thermal hotspots to minimize your design’s risk of field failure.

AC Analysis

Sigrity OptimizePI™ technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre-and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your PDN needs at the lowest possible cost. PDN impedance profiles are checked against target impedance constraints to ensure that the design meets PDN specifications.

Power-Ripple Analysis

The power ground noise simulation workflow from Sigrity SPEED2000™ technology can be used for direct time-domain power/ground noise simulation for the I/O power supply. Instead of having to extract S-parameter models and use them in a SPICE simulation, Sigrity Advanced PI provides a straightforward time-domain power integrity approach for either a PCB or IC package. It delivers a stable simulation result that would otherwise be more time consuming to obtain.

Sigrity Topology Explorer

This general-purpose topology exploration function can be used for exploring power topologies across multiple fabrics. By connecting the power ports of chip, package, and boards, you can create and simulate complete source-to-sink connectivity. PDN models for each fabric, created using the Sigrity PowerSI™ or Cadence Clarity™ 3D Solver, are excited using a model for the voltage regulator module (VRM). The resulting signal provides a time-domain view of the PDN voltage at each critical point from source to sink. You can determine if any portion of the PDN generates problems delivering power within the system specification.

Figure 2: The intuitive Sigrity topology explorer user experience makes it easy to join interconnect models for the PDN
across multiple boards, as well as chip and package, and see the impact to power stability

Features

  • Automatically set up DC simulations using PowerTree data (source/sink definitions) captured at the schematic stage of the design process
  • Identifies difficult-to-locate, highly resistive routing neck-downs and finds the one via among thousands that will fail under stress
  • Determines if it is possible to reduce plane layers without adding DC or thermal reliability risk
  • Reduces PDN cost for new designs and post-production products
  • Intuitive and interactive visualization of PDN performance

Contact Us

Hear how Seagate reduces IR drop and accelerates review cycles, while lowering product cost with Allegro and Sigrity tools

View a demo of Sigrity OptimizePI which provides an analytical basis for decisions regarding PDN design tradeoffs.

  • Related Links

    • Sigrity PowerDC
    • Sigrity OptimizePI
Videos

GLOBALFOUNDRIES: MCM LPDDR4 Analysis Accelerates Turnaround Time by 12X Using Sigrity SystemSI

Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives

DesignCon 2017: Sigrity 2017 Portfolio Highlights

Sigrity Tech Tip: How PCB Designers Can Create Initial PDN Constraints Without Becoming a PI Expert

Sigrity Tech Tip: How to Build an IBIS-AMI Model

Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

Sigrity Tech Tip: How PCB Designers Can Find and Fix Power Integrity Problems

Multi-Board Electrical and Thermal Co-simulation using Sigrity PowerDC

Why Does Signal Integrity Analysis Need to be Power-Aware?

Simulation of the Automotive Ethernet using Cadence Sigrity tools

Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk

News ReleasesVIEW ALL
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks 12/01/2015

Blogs VIEW ALL

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