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  • Sigrity Broadband SPICE

Sigrity Broadband SPICE

Accurately convert network parameters to SPICE-compatible circuits

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Key Benefits

  • Fast, easy model creation from N-port passive parameters for HSPICE and SPICE simulators
  • Reduces simulation issues and accelerates transient simulation runtimes
  • Accepts Touchstone or Sigrity BNP files

To reduce simulation issues and accelerate your transient simulation runtimes, Cadence® Sigrity™ Broadband SPICE™ technology accurately and quickly converts N-port passive-network parameters such as scattering, impedance, or admittance (S, Z, or Y) into SPICE-equivalent circuits that can be used in time-domain simulations. You can feed it data from Touchstone files and also from the more-compact Cadence Broadband Network Parameter (BNP) format.

Sigrity Broadband SPICE technology gives you a passive compact circuit model while maintaining accuracy for efficient transient simulations in HSPICE, or other SPICE-compatible circuit simulators, including the Sigrity SPEED2000™ time-domain simulator. The resulting compact black-box models created by Broadband SPICE give you excellent convergence.

Features

  • Generates models for DC through broadband frequencies
  • Extracts network models with multiple resonance points
  • Models a broad range of structures including IC packages, RF components, PCBs, cables, and connectors
  • Assesses real-world situations such as parallel traces traversing a split plane, spiral inductors, and return path discontinuities
  • Generates a very high order, but numerically stable, model for complex network responses
  • Enables analysis of PI/SI issues such as what-if optimization of power delivery system performance and simultaneous switching output simulation
  • Rigorous passivity enforcement assured by automated techniques along with interactive user review and control
  • Automatic determination of topology and circuit order based on network parameter curve complexity
  • Flexible to support flows where the target simulator may vary and where models are provided to others

REQUEST A DEMO

  • Related Products

    • Allegro Sigrity Power-Aware SI Option
    • Allegro Sigrity Serial Link Analysis Option
Resource Library VIEW ALL

Press Releases (6)

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis
  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff
  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces
  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks
  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options

Success Story Video (1)

  • Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Video (1)

  • Lattice Saves Millions, Avoids Respins and Product Delays with Sigrity Tools

Conference Paper (3)

  • Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card Conference Paper
  • Baseband IC Design Kits for Rapid System Realization
  • Channel Based Methods for Signal Integrity Evaluation Conference Paper

Presentation (1)

  • How to Efficiently Analyze a DDR4 Interface
News ReleasesVIEW ALL
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks 12/01/2015

BlogsVIEW ALL
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