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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
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        • Arm-Based Solutions
        • Cloud Solutions
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        • Hyperscale Computing
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Stratus High-Level Synthesis

Cuts IP development from months to weeks

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Key Benefits

  • 10X faster time to high-quality RTL
  • Up to 50% lower power
  • Up to 25% less area
  • Easy design closure

With Cadence® Stratus™ High-Level Synthesis (Stratus HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract IEEE 1666 synthesizable SystemC®, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.​

Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-written RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.​

With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment. ​

Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.

ASK US A QUESTION

 

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.

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WEBINAR

AI Accelerator Design
with Stratus™ HLS
(sign-in required)

VIEW WEBINAR

Hear how in only three months Ph. D student Myung-Seok Shim was able to learn how to take a TensorFlow machine learning model for image recognition to RTL using Stratus High-Level Synthesis.

  • Related Products

    • Genus Synthesis Solution
    • Joules RTL Power Solution
  • Related Links

    • How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
    • Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
    • How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
Videos

EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis

Designing a “First-Time-Right” Wi-Fi HaLow Baseband in less than 6 Months

From TensorFlow to RTL in three months

Designing an Automotive Graphics Display Controller with Stratus HLS

A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets

Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

Resource Library

Customer Presentation (9)

  • HLS Enables ML-Assisted Architectural Exploration
  • High-Level Synthesis Models in Pre-Silicon Verification
  • Coverage Closure for HLS-Based Design IP
  • Entering the World of High Level Synthesis: What We Have Learned and Experienced
  • FED102 - Design implementation of technology IP using High-Level Synthesis
  • DSG02 : Latency-Constrained Design of a Display Stream Compression Decoder using Stratus HLS
  • Stratus-Joules Solutions: Achieving Energy-Efficient Allocation
  • Designing an Automotive Graphics Display Controller with Stratus HLS
  • 0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design Solutions

White Paper (3)

  • How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
  • Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
  • Case Study: Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology White Paper

Conference Paper (1)

  • FED102 - Design implementation of technology IP using High-Level Synthesis

Webinar (1)

  • EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis

Video (8)

  • UCLA leverages high-level synthesis to make rapid architecture trade-offs
  • Stratus-Joules Solutions: Achieving Energy-Efficient Allocation
  • EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis
  • Whiteboard Wednesdays - Low-Power SoC Design with High-Level Synthesis
  • Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis
  • Designing an Automotive Graphics Display Controller with Stratus HLS
  • From TensorFlow to RTL in three months
  • A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets

Presentation (2)

  • High-Level Synthesis Will Supercharge Your IP Development
  • HLS-Based Design Space Exploration for Low-Power Designs

Press Releases (1)

  • Cadence Announces Stratus High-Level Synthesis Platform
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Digital Full Flow Achieves Certification for GlobalFoundries® 12LP/12LP+ Process Platforms 05/19/2022

  • Cadence’s John Wall and Richard Gu to Present at Needham Conference 05/06/2022

  • Cadence Reports First Quarter 2022 Financial Results 04/25/2022

  • Cadence Ushers in New Era of Performance and Accuracy for Multiphysics System Simulation with Fidelity CFD 04/19/2022

  • New Cadence High-Speed Ethernet Controller IP Family Enables Silicon-Proven Ethernet Subsystem Solutions up to 800Gbps 04/12/2022

Blogs VIEW ALL
Customers

With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously.

Ray McConnell, CTO, Blu Wireless Technology

Read More or View All Customers

Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge. By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively.

Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech

Read More or View All Customers

Using [the] HLS design flow we got an average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL.

Masato Tatsuoka, Socionext Inc.

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