WEBINAR
AI Accelerator Design
with Stratus™ HLS
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Key Benefits
- 10X faster time to high-quality RTL
- Up to 50% lower power
- Up to 25% less area
- Easy design closure
With Cadence® Stratus™ High-Level Synthesis (Stratus HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract IEEE 1666 synthesizable SystemC®, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.
Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-written RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.
With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment.
Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.
Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.
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Related Links
- How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
- Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
- How the Productivity Advantages of High-Level Synthesis Can Improve IP Design, Verification, and Reuse White Paper
Resource Library
Customer Presentation (9)
- HLS Enables ML-Assisted Architectural Exploration
- High-Level Synthesis Models in Pre-Silicon Verification
- Coverage Closure for HLS-Based Design IP
- Entering the World of High Level Synthesis: What We Have Learned and Experienced
- FED102 - Design implementation of technology IP using High-Level Synthesis
- DSG02 : Latency-Constrained Design of a Display Stream Compression Decoder using Stratus HLS
- Stratus-Joules Solutions: Achieving Energy-Efficient Allocation
- Designing an Automotive Graphics Display Controller with Stratus HLS
- 0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design Solutions
White Paper (3)
- How High-Level Synthesis Was Used to Develop an Image-Processing IP Design from C++ Source Code White Paper
- Using High-Level Synthesis to Design and Verify 802.11ah Baseband IP White Paper
- Case Study: Blu Wireless Boosts SystemC Design and Verification Productivity Using High-Level Synthesis Technology White Paper
Conference Paper (1)
Video (8)
- UCLA leverages high-level synthesis to make rapid architecture trade-offs
- Stratus-Joules Solutions: Achieving Energy-Efficient Allocation
- EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis
- Whiteboard Wednesdays - Low-Power SoC Design with High-Level Synthesis
- Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis
- Designing an Automotive Graphics Display Controller with Stratus HLS
- From TensorFlow to RTL in three months
- A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets
Presentation (2)
Press Releases (1)
Customers
With our high-level synthesis flow and the Stratus platform, we're now doing the kinds of things that we couldn't have imagined doing previously.
Ray McConnell, CTO, Blu Wireless Technology
Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge. By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively.
Masao Nakano, Design Engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech
Using [the] HLS design flow we got an average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL.
Masato Tatsuoka, Socionext Inc.
Training
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