Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Achieve industry’s fastest runtimes on a single machine or in the cloud
- Capacity to time over 1B instances flat with unique DSTA for full-chip signoff
- Speed design closure time by 3X and save up to 5% dynamic power Tempus ECO tightly integrated with Innovus Implementation System for physically aware timing and power optimization
- Find IR drop failures missed by traditional flows at 7nm and below with Tempus Power Integrity’s STA-aware IR drop analysis
- Fully certified down to 5nm at leading foundries, including early 3nm designs
- 5X faster runtime with CMMMC technology
- Streamline flow development and simplify user trainings with new Common User Interface shared across the Cadence digital full flow
- Accurate modeling of ultra-low voltage effects below 0.5V with advanced SI and SOCV; supports both Cadence SOCV library format and Liberty Variation Format (LVF)
- Faster runtime and reduced memory with SmartScope hierarchical abstraction and boundary models providing the same accuracy as flat STA
- Supports mixed-signal design through integration with Virtuoso Open Access database
The Cadence® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry today with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.
With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types: from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.
The Tempus solution is designed to tackle the most advanced timing requirements including full signal integrity (SI) analysis, glitch analysis and propagation, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static and dynamic power reduction, and hierarchical timing models.
More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.
The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff.
Jacques Martinella, Vice President, Engineering, Sigma Designs
The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs.
Toru Hiyama, General Manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.
The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab.
Lawrence Tse, Vice President of Engineering, Inphi
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview