In-Design Layout Optimization to Increase Manufacturability and Yield
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Key Benefits
- Improves systematic and parametric yield
- Meets DFM foundry requirements
- Integrates with Cadence custom and digital design platforms
The Cadence® Pegasus™ Layout Pattern Analyzer (LPA) quickly detects and automatically fixes lithography hotspots, based on either fast pattern matching and/or machine learning (ML) prediction.
Pegasus LPA detects manufacturability issues missed by traditional physical verification. Depending on the foundry enablement, the tool can either perform a pattern-based check to identify known hotspots or use a ML engine to predict unknown yield-limiting hotspots. Pegasus LPA not only provides foundry-certified fast-litho hotspot detection for signoff using pattern matching and/or ML, it also allows hotspots to be detected during implementation through tight integration with Cadence custom and digital implementation platforms. Integration with the Innovus™ Implementation System delivers a command-line interface with the Innovus DFM option where users can seamlessly invoke Pegasus LPA in scripts and use the fixing guidelines to increase automated fixing rates. The integration of Pegasus LPA through the framework included in the Virtuoso Application Library Environment offers a friendly environment for designers to accomplish DFM tasks. Pegasus LPA is a signoff for most foundries enforcing mandatory DFM checks.
In addition to DFM checks, Pegasus LPA can perform pattern-based layout optimization (PBLO) to improve design quality, increase usage of DFM rules, and automate the fixing of complex design rules.
Key Features
- Provides fast, scalable, and foundry-certified detection of yield-limiting hotspots to meet DFM signoff requirements
- Pegasus LPA with ML technology provides greater detection efficiency with minimal runtime impact
- Produces fixing guidelines to increase automated fixing rates and minimize design change
- Integrates with current library, IP, custom analog, and cell-based digital physical design flows
- Delivers versatile pattern-based layout optimization to improve design quality
Figure 1: Pegasus LPA integrated in Virtuoso environment
Figure 2: Pegasus LPA integrated in Innovus Implementation
Resource Library
Press Releases (9)
- Cadence and UMC Collaborate on 22ULP/ULL Reference Flow Certification for Advanced Consumer, 5G and Automotive Designs
- Cadence Delivers Automotive Reference Flow for Samsung Foundry 14LPU Process Technology
- GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design
- Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
- Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU
- Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology
- Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology
- Cadence and SMIC Collaborate on Delivery of Low-Power 28nm Digital Design Reference Flow
- Cadence Digital and Signoff Tools Certified on Samsung Foundry's 14LPP Process
Video (4)
Customer Presentation (7)
- Samsung 5LPE High Performance Implementation with Arm® Cortex®-A78 Processors Using Cadence Digital Flow
- Automated DfM Optimization Using Pattern Matching in Virtuoso and Innovus Solutions
- Implementation Challenges of a Design with 15M Instances in 14nm
- A Custom RISC-V SoC in GF 12LP Technology Designed with a Personalized Stylus Common UI Flow
- Design for Manufacturability (DFM) for the Custom/Analog Design Flow
- Managing Multiple Big Projects with a Small Team Using a Cadence Digital Flow
- Samsung Foundry DFM Flow with Cadence and Next Generation DFM Solution with Machine Learning Presentation
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