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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
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        • Arm-Based Solutions
        • Cloud Solutions
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        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
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        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
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        • Cloud Solutions
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        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
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        • Hyperscale Computing
      • Technologies
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        • Arm-Based Solutions
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Pegasus CMP Predictor

Predict and reduce systematic and parametric variability at chip- and wafer-level due to CMP-induced topography and layer thickness variations

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Key Benefits

  • Accurately predicts multi-layer thickness and topography variability for the entire layer stack using a model-based approach developed using Pegasus CMP Calibrator and Process Optimizer (Pegasus CCPO)
  • Detects hotspots that affect yield and produces fixing guidelines during implementation through integration with Virtuoso Layout Suite and Innovus Implementation System at block, chip, and wafer level
  • Interfaces with Quantus Extraction Solution to identify timing-related problems and potentially reduce process guardbands
  • Enables CMP teams to detect CMP hotspots on incoming designs, optimize CMP manufacturing parameters, and improve overall wafer-scale systematic and parametric variations

The Cadence® Pegasus™ CMP Predictor predicts chemical and mechanical polishing (CMP) variations and their potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing process variation into predictable impacts and then minimizes these impacts during dummy fill definition and at the design stage to greatly enhance overall design performance and yield. Traditionally used at the chip level, Pegasus CMP is also applicable at the IP level with its unique block-based methodology and at the wafer level with advanced wafer-scale modeling and prediction. Pegasus CMP provides wafer-scale, full-chip, multi-level thickness and topography predictions for the entire stack, covering FEOL, MOL, and BEOL deposition, etch, and planarization processes.

CMP-related hotspots, such as copper pooling, can have detrimental effects on wafer and chip yield. The conventional rules-based approach to hotspot detection fails to capture long-range and multi-level CMP effects. Pegasus CMP uses a highly accurate model-based approach to find potential hotspot areas. It also feeds the thickness and topography variation data into extraction tools, enabling better RC and timing analysis. The Pegasus CMP thickness and topography variation output is also used to compare different dummy fill strategies and to optimize dummy fill approaches.

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Pegasus CMP integrates with the Cadence Virtuoso® Layout Suite and Cadence Innovus™ Implementation System, and interfaces closely with the Cadence Quantus™ Extraction Solution for a complete silicon signoff solution.

Image of CMP Predictor and various graphs
CMP Predictor

Pegasus CCPO is used by CMP, process, DFM, or PDK teams to develop CMP models used by Pegasus CMP. The model calibration is done from silicon thickness measurements and creates semi-physical models that accurately model silicon trends and topography variations. Pegasus CCPO has dedicated versions and modeling capabilities for deposition, etch, and planarization processes in FEOL, MOL, and BEOL. Pegasus CCPO supports many advanced CMP process features such as reverse etch back and deposition angle, as well as specialized process flows such as those used in CMOS image sensors, 3D NAND, copper-to-copper packaging, or other 3D-IC manufacturing. It now also includes wafer-level calibration and prediction capabilities.

With prediction and optimization capabilities at chip and wafer-level, Pegasus CCPO is used by CMP process and product teams to detect potential hotspots or yield limiting issues in new products coming to the manufacturing line, and to optimize the CMP process parameters for a specific product layout. Pegasus CCPO improves the CMP efficiency and yield for each product at the chip or wafer level.

cmp-process-optimizer
Pegasus CMP Calibration and Process Optimization Viewer


file
Pegasus CMP Calibration and Process Optimization Wafer-Level Prediction

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SMIC describes the joint effort of SMIC with Cadence in creating DFM-clean libraries and accurate IP, CMP, and litho models for their worldwide customer base.

  • Related Products

    • Pegasus Computational Pattern Analytics
    • Pegasus Critical Area Analyzer
    • Pegasus Layout Pattern Analyzer
    • Process Proximity Compensation
News ReleasesVIEW ALL
  • Cadence Delivers Automotive Reference Flow for Samsung Foundry 14LPU Process Technology 04/08/2021

  • Cadence Collaborates with Arm and Samsung Foundry on Delivery of 5LPE Flow for Mission-Critical Applications Using Next-Generation “Hercules” CPU 10/08/2019

  • Cadence Digital Full Flow Achieves Certification for Samsung Foundry 5LPE Process Technology 07/02/2019

  • Cadence CMP Process Optimizer Enables Toshiba Memory Corporation to Accelerate Delivery of Advanced 3D Flash Memory Devices 02/25/2019

  • Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung’s 10nm Process Technology 10/24/2016

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Customers

The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation, and closure so we could quickly deliver a quality reference design to market.

Shih Chin Lin, Senior Division Director, IP Development and Design Support Division, UMC

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Working together with Cadence, we’re driving advances in CMP process performance.

Derek Witty, Vice President and General Manager, CMP Products Group, Applied Materials

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After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs.

Hiroshi Ikeda, Director of the System LSI Technology and Design Platform Development Department, Fujitsu Semiconductor Limited

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