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  • Liberate Variety Statistical Characterization

Liberate Variety Statistical Characterization

Fast, accurate process variation characterization

Liberate Variety Statistical Characterization Datasheet

Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper

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Key Benefits

  • Creates variation-aware timing models that account for both systemic process variations and random process variations
  • Includes tool libraries for modeling both local and global variations
  • Enables SSTA or conventional static timing analysis

ASK US A QUESTION

 

The Cadence® Liberate™ Variety™ statistical characterization solution provides an ultra-fast standard cell characterization of process-variation-aware timing models. Liberate Variety characterization generates libraries that can be used with multiple SSTAs without requiring re-characterization for each unique format. Variety characterization also generates AOCV and SOCV tables and LVF.

Features
  • Creates variation-aware timing models that account for both systematic process variations (e.g., variations due to lithography) and random process variations for any set of correlated or uncorrelated process parameters (e.g., variations due to doping fluctuations between transistors)
  • Tool libraries can be used to model both local (within cell and within die) variations and global die-to-die variations
  • Enables SSTA or conventional static timing analysis with on-chip variation tables to provide a more realistic estimation of timing relative to actual silicon performance, which often reduces worst-case timing margins by 10-15%, resulting in a higher yielding design that can be taped out sooner

REQUEST A DEMO

  • Related Products

    • Spectre Accelerated Parallel Simulator
    • Liberate LV Library Validation Solution
    • Liberate Variety Statistical Characterization
    • Spectre Circuit Simulator
    • Liberate Characterization Solution
    • Liberate AMS Mixed-Signal Characterization
    • Spectre eXtensive Partitioning Simulator (XPS)
  • Related Information

    • Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning White Paper
Videos

Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution

Ultra-Low Voltage SRAM: Addressing the Characterization Challenge

Liberate MX Product Demonstration

Characterizing 22FDX Library at GLOBALFOUNDRIES

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

News ReleasesVIEW ALL
  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies 09/25/2019

  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms 09/22/2016

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