Home
  • 제품소개
  • 솔루션
  • 기술지원 및 교육
  • 회사소개
  • KO KR
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • China - 简体中文
    • Japan - 日本語
    • Taiwan - 繁體中文

DESIGN EXCELLENCE

  • Digital Design and Signoff
  • Custom IC
  • Verification
  • IP
  • IC Package

SYSTEM INNOVATION

  • System Analysis
  • Embedded Software
  • PCB Design

PERVASIVE INTELLIGENCE

  • AI / Machine Learning
  • AI IP Portfolio

CADENCE CLOUD

Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

  • Logic Equivalence Checking
  • Innovus Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test
  • Flows
  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
  • Address digital implementation challenges with machine learning Watch Now

Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions
  • Flows
  • Solve analog simulation challenges in complex designs Watch Now
  • See how the Virtuoso Design Platform addresses advanced custom IC and system design challenges Watch Now

System Design and Verification

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

  • Debug Analysis
  • Emulation
  • Formal and Static Verification
  • FPGA-Based Prototyping
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP
  • Flows
  • Prototype your embedded software development Watch Now
  • Learn how early firmware development enabled first silicon success at Toshiba Memory Watch Now

IP

An open IP platform for you to customize your app-driven SoC design.

  • Interface IP
  • Denali Memory IP
  • Tensilica Processor IP
  • Analog IP
  • System / Peripherals IP
  • Verification IP
  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
  • Meeting the needs of 5G communication with Tensilica® ConnX B20 DSP IP Download Now

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows
  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Thermal Solutions
  • System Analysis Resources Hub

Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • What's New in Allegro
  • What's New in Sigrity
  • RF / Microwave Design
  • Flows
  • Advanced PCB Design & Analysis Blog
  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
  • Augmented Reality Lab Tools

AI / Machine Learning

AI IP Portfolio

INDUSTRIES

  • 5G Systems and Subsystems
  • Aerospace and Defense
  • Automotive
  • AI / Machine Learning

TECHNOLOGIES

  • 3D-IC Design
  • Advanced Node
  • Arm-Based Solutions
  • Cloud Solutions
  • Low Power
  • Mixed Signal
  • Photonics
  • RF / Microwave
See how our customers create innovative products with Cadence Explore Now

SUPPORT

  • Support Process
  • Online Support
  • Software Downloads
  • Computing Platform Support
  • Customer Support Contacts
  • Technical Forums

TRAINING

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
  • Digital Design and Signoff
  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
Stay up to date with the latest software Download Now
24/7 - Cadence Online Support Visit Now

CORPORATE

  • About Us
  • Designed with Cadence
  • Investor Relations
  • Leadership Team
  • Computational Software
  • Alliances
  • Corporate Social Responsibility
  • Cadence Academic Network

MEDIA CENTER

  • Events
  • Newsroom
  • Blogs

CULTURE AND CAREERS

  • Culture and Diversity
  • Careers
Learn how Intelligent System Design™ powers future technologies Learn More
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
View all Products
  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • Custom IC / Analog / RF Design
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • System Design and Verification
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC Package Design and Analysis
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • System Analysis
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • Embedded Software
      • PCB Design and Analysis
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
  • 솔루션
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • AI / Machine Learning
      • TECHNOLOGIES
        • 3D-IC Design
        • Advanced Node
        • Arm-Based Solutions
        • Cloud Solutions
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • SUPPORT
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • TRAINING
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • 회사소개
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers
      • CORPORATE
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • MEDIA CENTER
        • Events
        • Newsroom
        • Blogs
      • CULTURE AND CAREERS
        • Culture and Diversity
        • Careers

Liberate Trio Characterization Suite

Industry’s first complete library characterization system

Read Datasheet
  • Liberate Trio Characterization Suite
  • Characterization
  • Process Variation Modeling
  • Library Validation

Key Benefits

  • Comprehensive library characterization system including variation modeling and library validation for standard cells and complex I/Os
  • Ability to characterize multi-PVT corners in the same run
  • Generate statistical libraries in LVF along with nominal using the unified flow
  • Critical corner prediction using machine learning algorithms
  • Cloud enablement with massive distribution and parallelization algorithms for faster throughput
ASK US A QUESTION

 

The Cadence® Liberate™ Trio Characterization Suite is the industry’s first unified library characterization system that brings together characterization, variation modeling, and library validation for standard cells, custom cells, multi-bits, and I/Os. The Liberate Trio Suite includes multi-PVT and unified flows that achieve both accuracy and high-speed performance. Its powerful combination of patented technology for generating and optimizing characterization stimulus and parallel processing capability takes advantage of enterprise-wide compute resources, and it leverages cloud resources for an enormous collection of libraries. The Liberate Trio suite is your one-stop-shop for all aspects of standard cell library characterization and validation.

Unified Library Characterization System

The Liberate Trio suite combines our tested and proven characterization suite with some of the most advanced technology available today in a unified library characterization system.

Liberate Trio Characterization Suite complete library characterization system

Multi-PVT Flow

The Liberate Trio suite provides a new multi-PVT flow to characterize multiple corners in the same run with the resulting libraries maintaining consistency in structure. Vectors and modeling attributes extracted from standard cell circuit analysis are shared among all corners to reduce runtime and ensure the structural symmetry need for static timing analysis (STA) scaling applications. This simplifies the challenge of dealing with an enormous collection of corners across libraries.

Unified Flow

Statistical libraries in Liberty Variation Format (LVF) and nominal libraries can now be generated using a unified characterization run that shares statistical and nominal SPICE process models. This flow eliminates the need to merge libraries at the end of a statistical run and the combined characterization run improves performance.

Machine Learning

The machine learning algorithms in the Liberate Trio suite enable prediction of critical corners through clustering techniques to determine which corners need to be characterized. The use of machine learning significantly reduces the number of libraries that will need to be characterized while ensuring accuracy using smart interpolation.

Cloud Enablement

Characterization of large libraries that would normally take weeks can now be turned around in days. Thoroughly distributed and massively parallel, our library characterization portfolio has been fully optimized to run on cloud-based servers by making characterization processes. The Liberate Trio suite can be used on leading cloud service providers or a company’s private cloud, and is scalable to over thousands of CPUs. 

Features

  • Utilizes a single script to characterize all PVT corners in a library using multi-PVT flow
  • Statistical and nominal libraries unified in a single characterization run
  • Efficient multiprocessing delivers 3X runtime improvements for library sets
  • Predicts critical corners using machine learning 
  • Runtime metrics and results monitoring with a sleek new GUI cockpit

GlobalFoundries’ Siddharth Sawant shares insights on the aging mechanisms and best approach to achieve highly accurate aging data models using the Cadence Liberate Characterization Solution.

Hear how the cloud-optimized Liberate Trio Characterization Suite provides characterization, process variation modeling, and validation for improved throughput and productivity.

Advanced Characterization with Cadence Liberate Trio

  • Related Pages

    • Liberate MX Memory Characterization
    • Liberate AMS Mixed-Signal Characterization
Resource Library

Video (10)

  • Advanced Characterization with Cadence Liberate Trio Characterization Suite
  • GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications
  • Overview of the Characterization Interface in Liberate Trio Characterization Suite
  • Achieve greater throughput and productivity with Liberate Trio Characterization Suite
  • Library Characterization in the Cloud
  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Faster Timing Characterization of Analog Macros
  • Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization
  • Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

Success Story Video (3)

  • Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution
  • Characterizing 22FDX Library at GLOBALFOUNDRIES
  • Faster Timing Characterization of Analog Macros

Datasheet (1)

  • Liberate Trio Characterization Suite Datasheet

Press Releases (9)

  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production

White Paper (2)

  • Compressing Datasets Created During Silicon Design White Paper
  • Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper

Presentation (1)

  • Quantus Extraction Solution for Accurate and Fast Silicon Signoff and Verification
VIEW ALL
Videos

Overview of the Characterization Interface in Liberate Trio Characterization Suite

Achieve greater throughput and productivity with Liberate Trio Characterization Suite

GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications

Cadence Cloud for Characterization

Liberate MX Product Demonstration

Characterizing 22FDX Library at GLOBALFOUNDRIES

Faster Timing Characterization of Analog Macros

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

Advanced Characterization with Cadence Liberate Trio Characterization Suite

News ReleasesVIEW ALL
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design 04/22/2019

  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations 06/25/2018

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

Blogs VIEW ALL

A Great Place to Do Great Work!

Sixth year on the FORTUNE 100 list

Our Culture Join The Team
  • Products
  • Custom IC and RF
  • Digital Design and Signoff
  • IC Package
  • IP
  • PCB Design
  • System Analysis
  • Verification
  • All Products
  • Company
  • About Us
  • Leadership Team
  • Investor Relations
  • Alliances
  • Careers
  • Cadence Academic Network
  • Supplier
  • Media Center
  • Events
  • Newsroom
  • Designed with Cadence
  • Blogs
  • Forums
  • Contact Us
  • General Inquiry
  • Customer Support
  • Media Relations
  • Global Office Locator

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2021 Cadence Design Systems, Inc. All Rights Reserved.

Terms of Use Privacy US Trademarks
Connect with us