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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Multiphysics System Analysis

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Embedded Software

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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Computational Fluid Dynamics

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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Liberate AMS Mixed-Signal Characterization

Offers 20X faster characterization of post-layout netlists

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Key Benefits

  • Unparalleled operational efficiency and user flexibility with highly scalable systems
  • Advanced compiler, predictable runtime, and debug capabilities
  • Offers 20X faster characterization of post-layout netlists
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
ASK US A QUESTION

 

Cadence® Liberate™ AMS mixed-signal characterization solution enables fast and accurate characterization of large mixed-signal macros to create instance-specific memory models for timing, power, and noise.

The Liberate AMS solution extends Cadence’s ultra-fast standard cell and I/O library characterization capabilities to cover large mixed-signal macro blocks such as phase-locked loops (PLLs), data converters (ADCs, DACs), SerDes, high-speed transceivers, and high-speed I/Os. Macro blocks require additional pre-analysis steps in order to make fast and accurate characterization feasible. Leveraging a network of distributed CPUs and utilizing the “hybrid partitioning” technology for optimizing characterization runtime, mixed-signal macros can be characterized quickly and easily with the same accuracy and methods as standard cells, including the generation of timing constraints and modeling of current source models for timing, power, and noise.

Automotive TCL1 Certified for ISO 26262

The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Features

  • Automates the creation of standard Liberty models for large mixed-signal macro blocks by automatically capturing the interaction between digital and analog paths to identify latches, flops, and other probe nodes
  • Improved throughput comes from “hybrid partitioning” technology, comprised of a full-block view and partitioned sub-block views to characterize large macro blocks efficiently and accurately
  • Full-block view is used to characterize power and drive the creation of sub-block partitions
  • Integrated with Virtuoso Analog Design Environment, enabling the reuse of test-benches and existing setup to quickly move from circuit design validation into library generation

Contact Us

The Liberate AMS characterization solution delivers 20X performance improvement versus traditional methods while maintaining true SPICE accuracy

  • Related Products

    • Liberate Trio Characterization Suite
    • Liberate MX Memory Characterization
    • Spectre Circuit Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Liberate Variety Statistical Characterization
    • Spectre Accelerated Parallel Simulator
  • Related Information

    • Addressing Process Variation and Reducing Timing Pessimism at 16nm and Below White Paper
Videos

Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Characterizing 22FDX Library at GLOBALFOUNDRIES

Liberate MX Product Demonstration

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

News ReleasesVIEW ALL
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations 06/25/2018

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

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