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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Embedded Software

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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Computational Fluid Dynamics

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KR - Korea
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  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
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      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
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Legato Memory Solution

Industry's first memory design, verification, and characterization solution

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Key Benefits

  • Shared engines across design and characterization ensure consistency of results
  • Better overall throughput through tight integration between different tools
  • One-stop shop for all memory design, verification, and characterization needs

On today’s SoC designs, the memory and memory arrays take up a lot of real estate and are often in the critical path for timing, yield, and schedule. Due to ever-increasing memory size demand, design and verification engineers are faced with multiple challenges, such as time to market due to an aggressive schedule, the use of different point tools such as SPICE and FastSPICE simulators, characterization utility, and the consistency that is required across the tools.

The Cadence® Legato™ Memory Solution is the industry’s first integrated solution for memory design, verification, and characterization. Eliminating the complexity of piecing together point tools for multiple design and verification tasks, Legato Memory Solution provides one platform for all memory design, verification, and characterization needs, maximizing the simulation throughput and leading to a 2X runtime improvement while maintaining the accuracy.

The new solution is built on the golden-, industry- and silicon-proven Spectre® and Liberate™ simulation and characterization engines and includes a new patent-pending Super Sweep technology that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, allowing designers to improve both runtime and simulation throughput.

custom-ic-legato-memory-solution-600px

Design Cockpits

The Cadence Legato Memory Solution consists of three environment cockpits: cell design, array and complier verification, and memory characterization. With the cell design cockpit, engineers can design the bitcell and get Monte Carlo variation analysis. When accessing the array and compiler verification cockpit, design and verification of full memory arrays occurs while accessing new tools, like Super Sweep, to maximize accuracy and simulation throughput for advanced-node designs. Finally, in the memory characterization cockpit, a Liberty library format of the memory is created and can used for SoC full-chip analysis.

This one-of-a-kind solution gives engineers a cohesive design environment that automates design steps, ensures consistency, and allows designers to use the Cadence toolset to deliver products to market faster. With the Cadence Legato Memory Solution, designers can improve productivity while meeting demanding design schedules. View our Legato Memory Solution videos for more details on the solution.

Contact Us

Learn about how the Legato Memory Solution provides a one-stop shop for memory design, verification, and characterization.

  • Related Products

    • Spectre Circuit Simulator
    • Liberate MX Memory Characterization
    • Spectre Accelerated Parallel Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
Videos

Increase Your Productivity with Cadence Legato Memory Solution

Cadence Legato Memory Solution Verification Overview

Legato Memory Solution Characterization Overview

Fast & Efficient Memory Verification and Characterization for Advanced On Chip Variation

News ReleasesVIEW ALL
  • M31 Speeds Delivery of Silicon IP by 5X Using the Cadence Library Characterization Solution in the Cloud 03/30/2022

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Samsung Foundry Adopts Cadence Liberate Trio Characterization Suite for 3nm Production Library 11/16/2021

  • Samsung Foundry Adopts New Tempus SPICE-Accurate Aging Analysis for High-Reliability Applications 11/16/2021

  • Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric™ Technologies for Advanced Multi-Chiplet Designs 10/26/2021

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