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Digital Design and Signoff

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
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  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Cerebrus Intelligent Chip Explorer
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Custom IC / Analog / RF Design

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
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  • Layout Design
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  • Library Characterization
  • RF / Microwave Solutions

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  • Spectre X Simulator
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Verification

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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  • Debug Analysis
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FEATURED PRODUCTS

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IP

An open IP platform for you to customize your app-driven SoC design.

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  • Denali Memory Interface and Storage IP
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RESOURCES

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IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Multiphysics System Analysis

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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  • Computational Fluid Dynamics
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FEATURED PRODUCTS

  • Clarity 3D Solver
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Embedded Software

PCB Design and Analysis

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
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  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
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  • What's New in Allegro
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Computational Fluid Dynamics

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AI IP Portfolio

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KR - Korea
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  • Taiwan - 繁體中文
  • 제품소개
    • DESIGN EXCELLENCE
      • Digital Design and Signoff
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • Custom IC / Analog / RF Design
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC Package Design and Analysis
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • Flows
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
    • SYSTEM INNOVATION
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • Embedded Software
      • PCB Design and Analysis
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
      • AI / Machine Learning
      • AI IP Portfolio
    • CADENCE CLOUD
    • VIEW ALL PRODUCTS
  • 솔루션
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
      • Industries
        • 5G Systems and Subsystems
        • Aerospace and Defense
        • Automotive
        • Hyperscale Computing
      • Technologies
        • 3D-IC Design
        • Advanced Node
        • AI / Machine Learning
        • Arm-Based Solutions
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • Low Power
        • Mixed Signal
        • Photonics
        • RF / Microwave
  • 기술지원 및 교육
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Virtuoso Analog Design Environment

Advanced design simulation for fast and accurate verification

Read Datasheet Read Datasheet
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  • Support and Training

Key Benefits

  • Reduced learning curve with a simulator-independent environment
  • Maximum efficiency in the script-driven mode
  • Accelerated debug process using a variety of built-in analog analysis tools
  • Facilitated design correction via easy comparison of pre- and post-parasitic extracted designs
  • Quick detection of circuit problems via a clear visualization cockpit
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

Designed to help users create manufacturing-robust designs, the Cadence® Virtuoso® Analog Design Environment is the advanced design and simulation environment for the Virtuoso platform. It gives designers access to a new parasitic estimation and comparison flow and optimization algorithms that help to center designs better for yield improvement and advanced matching and sensitivity analyses. By supporting extensive exploration of multiple designs against their objective specifications, the Virtuoso Analog Design Environment sets the standard in fast and accurate design verification.

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre® Circuit Simulation Platform. The Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Contact Us

  • Related Products

    • Virtuoso ADE Assembler
    • Virtuoso ADE Product Suite
    • Virtuoso ADE Explorer
    • Virtuoso ADE Verifier
    • Spectre Accelerated Parallel Simulator
    • Virtuoso Schematic Editor
Resource Library

Press Releases (13)

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack | Cadence
  • Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications | Cadence
  • Tower Semiconductor and Cadence Announce New Reference Flow for Advanced 5G Communications and Automotive IC Development | Cadence
  • Cadence Collaborates with TSMC to Accelerate Mobile, AI and Hyperscale Computing Application Development on N3 and N4 Processes | Cadence
  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology | Cadence
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout | Cadence
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process | Cadence
  • Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology | Cadence
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform | Cadence
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow | Cadence
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs | Cadence
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes | Cadence
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry | Cadence

Video (5)

  • Celebrating 25 Years of Virtuoso Innovation
  • Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK
  • Transistor-Level Reliability Analysis for Advanced Node
  • Verifying the RTL in an Analog Circuit
  • Addressing MCU Mixed-Signal Design Challenges for SoCs and IoT

Webinar (2)

  • Addressing Smart Sensor Design Challenges for SoCs and IoT Webinar (IoT Webinar Series - Part 2)
  • Addressing Smart Sensor Design Challenges for SoCs and IoT (Part 1)

Success Story Video (1)

  • Transistor-Level Reliability Analysis for Advanced Node

Datasheet (6)

  • Virtuoso ADE Explorer Datasheet
  • Virtuoso Variation Option Datasheet
  • Cadence® Virtuoso® ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions.
  • Virtuoso Analog Design Environment GXL Datasheet
  • Virtuoso Analog Design Environment XL Datasheet
  • Virtuoso Analog Design Environment L Datasheet

Customers Success (3)

  • Moving to UVM-MS to Meet Coverage Goals Case Study
  • Cadence and Melexis Success Story
  • Cadence and Fuji Electric Success Story

White Paper (2)

  • Save Time and Minimize Errors by Automating Co-Design and Co-Analysis of Chips, Boards, and Packages
  • Plan-Based Analog Verification Methodology White Paper
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications 10/21/2021

  • Tower Semiconductor and Cadence Announce New Reference Flow for Advanced 5G Communications and Automotive IC Development 08/16/2021

  • Cadence Collaborates with TSMC to Accelerate Mobile, AI and Hyperscale Computing Application Development on N3 and N4 Processes 05/27/2021

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

Blogs VIEW ALL
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